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annotate venus/src/core/rita_vcxo_int.v @ 48:d55824058cfc

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LCD subsystem integrated
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 27 Nov 2021 02:46:19 +0000
parents 3ed0f7a9c489
children
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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2 * This module encapsulates the Rita block (Rita chip + caps) together with
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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3 * the choice of internal or external VC(TC)XO; this version is for the
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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4 * internal configuration.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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5 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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6
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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7 module rita_vcxo_int (GND, VBAT, VREG3, VRIO,
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8 TCXOEN, RFEN, AFC_in, Clock_out_to_DBB,
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9 Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ,
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10 IN, IP, QN, QP,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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11 LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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12 LBTXOUT, HBTXOUT,
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13 DAC, DET1, DET2, APC,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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14 RTEMP_VTEST);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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15
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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16 input GND, VBAT, VRIO;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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17 output VREG3;
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18
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19 input TCXOEN, RFEN, AFC_in;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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20 output Clock_out_to_DBB;
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21
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22 input Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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23 inout IN, IP, QN, QP;
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24
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25 input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
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26 output LBTXOUT, HBTXOUT;
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27
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Mychaela Falconia <falcon@freecalypso.org>
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28 input DAC, DET1, DET2;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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29 output APC;
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30
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31 output RTEMP_VTEST;
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32
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33 /* internal VCTCXO configuration */
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34
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35 wire XIN;
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36
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37 int_vcxo_passive vcxo_passive (AFC_in, XIN, GND);
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38
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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39 /*
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40 * Some Leonardo schematic versions show a "resistor short" with refdes R604
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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41 * between TCXOEN from the Calypso and the net going to XEN, XSEL and the cap
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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42 * or two caps. In Openmoko's version this component is a physical 0402 SMT
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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43 * 0R jumper; in iWOW TR-800 this series R has been measured to be 47 Ohm
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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44 * instead. On FC Venus we shall include an 0402 series R footprint
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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45 * just in case.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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46 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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47
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48 wire TCXOEN_after_0R;
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49
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50 resistor R604 (TCXOEN, TCXOEN_after_0R);
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51
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52 /* instantiate the Rita block */
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53
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54 rita_wrap rita (.GND(GND),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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55 .VBAT(VBAT),
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56 .VREG3(VREG3),
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57 .VRIO(VRIO),
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58 .XEN(TCXOEN_after_0R),
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59 .XSEL(TCXOEN_after_0R),
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60 .XIN(XIN),
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61 .Clock_out_to_DBB(Clock_out_to_DBB),
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62 .Ctrl_CLK(Ctrl_CLK),
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63 .Ctrl_DATA(Ctrl_DATA),
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64 .Ctrl_STROBE(Ctrl_STROBE),
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65 .Ctrl_RESETZ(Ctrl_RESETZ),
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66 .IN(IN),
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67 .IP(IP),
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68 .QN(QN),
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69 .QP(QP),
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70 .LNAGSMN(LNAGSMN),
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71 .LNAGSMP(LNAGSMP),
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72 .LNADCSN(LNADCSN),
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73 .LNADCSP(LNADCSP),
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74 .LNAPCSN(LNAPCSN),
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75 .LNAPCSP(LNAPCSP),
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76 .LBTXOUT(LBTXOUT),
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77 .HBTXOUT(HBTXOUT),
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78 .DAC(DAC),
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79 .DET1(DET1),
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80 .DET2(DET2),
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81 .APC(APC),
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82 .RTEMP_VTEST(RTEMP_VTEST)
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83 );
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84
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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85 endmodule