FreeCalypso > hg > freecalypso-schem2

annotate venus/src/core/rfmatch_rita2pa_lb.v @ 69:de44df15cf05

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MCL capacitors: convert to parts
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Dec 2021 07:20:13 +0000
parents 3ed0f7a9c489
children
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /* RF Tx path from Rita to PA, low bands */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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3 module rfmatch_rita2pa_lb (In, Out, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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4
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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5 input In;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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6 output Out;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 input GND;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 wire mid1, mid2;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 inductor L601 (In, mid1);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 capacitor C655 (mid1, mid2);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 chip_attenuator R600 (mid2, Out, GND, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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15 endmodule