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annotate venus/src/periph/MAX1916.v @ 68:ef00bcf4a7ee

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MCL: assign value to all capacitors
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Dec 2021 05:53:13 +0000
parents c247abb89302
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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46
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
Mychaela Falconia <falcon@freecalypso.org>
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1 module MAX1916 (GND, EN, SET, LEDK);
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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2
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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3 input GND, EN, SET;
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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4 output [1:3] LEDK;
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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5
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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6 /* instantiate the package; the mapping of signals to pins is defined here */
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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7
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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8 pkg_SOT23_6 pkg (.pin_1(EN),
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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9 .pin_2(GND),
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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10 .pin_3(SET),
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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11 .pin_4(LEDK[3]),
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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12 .pin_5(LEDK[2]),
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13 .pin_6(LEDK[1])
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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14 );
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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15
c247abb89302 MAX1916.v and lcd_module.v from lunalcd2
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16 endmodule