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annotate venus/src/periph/audio_hso.v @ 68:ef00bcf4a7ee

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MCL: assign value to all capacitors
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Dec 2021 05:53:13 +0000
parents 229f0b2dd1bf
children
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1 /*
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2 * This Verilog module encapsulates our secondary headset audio channel,
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3 * connected to Iota headset interface.
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4 */
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5
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6 module audio_hso (GND, Vio, HSMICBIAS, HSMICP, HSO, Detect);
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7
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8 input GND, Vio;
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9 input HSO, HSMICBIAS;
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10 output HSMICP, Detect;
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11
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12 /* internal wires */
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13
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14 wire EAR_jack, MIC_jack;
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15
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16 /* instantiate the jack */
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17
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18 trrs_jack jack (.T(GND),
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19 .R(MIC_jack),
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20 .R2(EAR_jack),
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21 .S(GND),
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22 .T_sw(Detect),
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23 .R_sw() /* not used */
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24 );
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25
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26 /* output path */
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27
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28 capacitor HSO_cap (HSO, EAR_jack);
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29
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30 /* microphone input circuit */
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31
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32 capacitor C37 (HSMICBIAS, GND);
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33 resistor R19 (HSMICBIAS, MIC_jack);
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34
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35 capacitor C38 (MIC_jack, GND);
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36
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37 capacitor C23 (MIC_jack, HSMICP);
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38 capacitor C22 (HSMICP, GND);
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39
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40 /* Detect pull-up resistor */
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41
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42 resistor Detect_pullup (Detect, Vio);
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43
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44 endmodule