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annotate venus/src/periph/audio_main.v @ 68:ef00bcf4a7ee

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MCL: assign value to all capacitors
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Dec 2021 05:53:13 +0000
parents 3afd172b83e1
children
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57
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1 /*
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2 * This Verilog module encapsulates our main audio channel.
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3 */
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4
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5 module audio_main (GND, EARN, EARP, MICBIAS, MICIN, MICIP);
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6
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7 input GND;
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8 input EARN, EARP;
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9 input MICBIAS;
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10 output MICIN, MICIP;
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11
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12 /* internal wires */
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13
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14 wire EARN_jack, EARP_jack, MIC_jack;
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15
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16 /* instantiate the jack */
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17
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18 trrs_jack jack (.T(EARP_jack),
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19 .R(MIC_jack),
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20 .R2(EARN_jack),
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21 .S(GND),
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22 .T_sw(), /* not used */
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23 .R_sw() /* not used */
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24 );
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25
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26 /* earpiece path filter caps */
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27
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28 capacitor C15 (EARP, EARN);
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29 capacitor C16 (EARP, GND);
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30 capacitor C17 (EARP, GND);
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31 capacitor C18 (EARN, GND);
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32 capacitor C19 (EARN, GND);
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33
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34 /* earpiece path filter inductors */
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35
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36 inductor L1 (EARP, EARP_jack);
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37 inductor L2 (EARN, EARN_jack);
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38
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39 /* microphone input circuit */
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40
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41 capacitor C13 (MICBIAS, GND);
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42
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43 resistor R9 (MICBIAS, MIC_jack);
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44 capacitor C14 (MIC_jack, GND);
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45
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46 capacitor C12 (MICBIAS, MICIP);
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47 capacitor C21 (MIC_jack, MICIN);
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48
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49 capacitor C32 (MICIP, MICIN);
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50
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51 endmodule