FreeCalypso > hg > freecalypso-schem2
annotate venus/src/usb/usb_domain_bctl.v @ 68:ef00bcf4a7ee
MCL: assign value to all capacitors
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Dec 2021 05:53:13 +0000 |
parents | 9309cebe07b8 |
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rev | line source |
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24
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Mychaela Falconia <falcon@freecalypso.org>
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1 /* |
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2 * This module encapsulates the USB domain circuit for boot control. |
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3 */ |
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Mychaela Falconia <falcon@freecalypso.org>
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4 |
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5 module usb_domain_bctl (GND, P_3V3, ChanB_RTS, ChanB_DTR, CTL1_out, CTL2_out); |
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Mychaela Falconia <falcon@freecalypso.org>
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6 |
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7 input GND, P_3V3; |
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Mychaela Falconia <falcon@freecalypso.org>
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8 input ChanB_RTS, ChanB_DTR; |
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Mychaela Falconia <falcon@freecalypso.org>
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9 output CTL1_out, CTL2_out; |
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10 |
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11 /* pull-up resistors on FT2232D outputs */ |
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Mychaela Falconia <falcon@freecalypso.org>
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12 |
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13 resistor ChanB_RTS_pullup (ChanB_RTS, P_3V3); |
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Mychaela Falconia <falcon@freecalypso.org>
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14 resistor ChanB_DTR_pullup (ChanB_DTR, P_3V3); |
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Mychaela Falconia <falcon@freecalypso.org>
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15 |
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16 /* open drain buffers */ |
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17 |
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18 logic_ic_common od_buf_common ( .Vcc(P_3V3), |
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19 .GND(GND) |
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20 ); |
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21 |
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22 capacitor od_buf_bypass_cap (P_3V3, GND); |
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23 |
40
9309cebe07b8
use buffer_slot_od primitive for slots of 74LVC2G07
Mychaela Falconia <falcon@freecalypso.org>
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24 buffer_slot_od buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out)); |
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use buffer_slot_od primitive for slots of 74LVC2G07
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25 buffer_slot_od buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out)); |
24
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26 |
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Mychaela Falconia <falcon@freecalypso.org>
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27 endmodule |