FreeCalypso > hg > freecalypso-schem2

annotate venus/src/usb/usb_xtal_wrap.v @ 68:ef00bcf4a7ee

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MCL: assign value to all capacitors
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Dec 2021 05:53:13 +0000
parents 8f3df7a222f5
children
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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2 * This Verilog module encapsulates the PCB footprint
8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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3 * for our 6.0 MHz USB crystal.
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
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8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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6 module usb_xtal_wrap (electrode1, electrode2, GND);
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 input electrode1, electrode2, GND;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
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8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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10 xtal_4pin_pkg xtal (.pin_1(electrode1),
8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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11 .pin_2(GND),
8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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12 .pin_3(electrode2),
8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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13 .pin_4(GND)
8f3df7a222f5 change USB 6.0 MHz crystal to a smaller part
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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14 );
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 endmodule