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annotate venus/src/core/M034F.v @ 65:fb8fceab632c

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venus/src/Makefile: unet-bind -c to check completeness
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 21:47:20 +0000
parents 3ed0f7a9c489
children
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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1 module M034F (ANT, GND, RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2,
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2 TX_LOW, TX_HIGH, V_TX_LOW, V_TX_HIGH, V_RX_850);
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3
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4 inout ANT;
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5 input GND;
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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7 output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2;
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8 input TX_LOW, TX_HIGH;
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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10 input V_TX_LOW, V_TX_HIGH, V_RX_850;
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11
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12 /* instantiate the package; the mapping of signals to pins is defined here */
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13
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14 pkg_M034F pkg (.pin_1(ANT),
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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15 .pin_2(GND),
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16 .pin_3(TX_HIGH),
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17 .pin_4(GND),
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18 .pin_5(GND),
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19 .pin_6(TX_LOW),
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20 .pin_7(V_TX_LOW),
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21 .pin_8(V_TX_HIGH),
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22 .pin_9(V_RX_850),
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23 .pin_10(RX_DCS1),
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24 .pin_11(RX_DCS2),
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25 .pin_12(RX_PCS1),
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26 .pin_13(RX_PCS2),
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27 .pin_14(RX_LOW1),
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28 .pin_15(RX_LOW2),
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29 .pin_16(GND),
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30 .pin_17(GND),
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31 .pin_18(GND),
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32 .pin_19(GND)
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33 );
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34
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35 endmodule