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annotate venus/src/core/RF3166.v @ 65:fb8fceab632c

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venus/src/Makefile: unet-bind -c to check completeness
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 21:47:20 +0000
parents 3ed0f7a9c489
children
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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1 module RF3166 (HB_RF_in, Band_Select, Tx_Enable, Vbatt, GND, Vramp, LB_RF_in,
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2 LB_RF_out, HB_RF_out);
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4 input LB_RF_in, HB_RF_in;
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5 input Band_Select, Tx_Enable;
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6 input GND, Vbatt, Vramp;
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7 output LB_RF_out, HB_RF_out;
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8
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9 /* instantiate the package; the mapping of signals to pins is defined here */
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11 pkg_RF3166 pkg (.pin_1(HB_RF_in),
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12 .pin_2(Band_Select),
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13 .pin_3(Tx_Enable),
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14 .pin_4(Vbatt),
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15 .pin_5(GND),
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16 .pin_6(Vramp),
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17 .pin_7(LB_RF_in),
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18 .pin_8(LB_RF_out),
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19 .pin_9(HB_RF_out),
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20 .pin_10(GND),
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21 .pin_11(GND),
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22 .pin_12(GND),
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23 .pin_13(GND),
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24 .pin_14(GND),
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25 .pin_15(GND),
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26 .pin_16(GND),
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27 .pin_17(GND),
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28 .pin_18(GND),
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29 .pin_19(GND),
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30 .pin_20(GND),
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31 .pin_21(GND),
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32 .pin_22(GND),
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33 .pin_23(GND),
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34 .pin_24(GND),
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35 .pin_25(GND),
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36 .pin_26(GND),
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37 .pin_27(GND),
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38 .pin_28(GND),
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39 .pin_29(GND),
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40 .pin_30(GND),
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41 .pin_31(GND)
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42 );
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43
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44 endmodule