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annotate venus/src/core/abb_rc_network.v @ 65:fb8fceab632c

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venus/src/Makefile: unet-bind -c to check completeness
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 21:47:20 +0000
parents 3ed0f7a9c489
children
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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2 * In the Leonardo schematics there is an RC network in the analog I&Q
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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3 * signal path between the uplink (BUL[IQ][MP]) outputs from the ABB
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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4 * and the bidirectional signals which connect directly to the RF xcvr
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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5 * and to Iota's downlink (BDL[IQ][MP]) inputs.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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6 *
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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7 * This structural Verilog module encapsulates the RC network in question.
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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8 */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 module abb_rc_network (IM_bidir, IP_bidir, QM_bidir, QP_bidir,
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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11 IM_abbout, IP_abbout, QM_abbout, QP_abbout);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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12
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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13 inout IM_bidir, IP_bidir, QM_bidir, QP_bidir;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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14 input IM_abbout, IP_abbout, QM_abbout, QP_abbout;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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15
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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16 wire IM_mid, IP_mid, QM_mid, QP_mid;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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18 /* resistors on the outputs from the ABB */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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19 resistor_slot R295A (IM_abbout, IM_mid);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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20 resistor_slot R295B (IP_abbout, IP_mid);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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21 resistor_slot R295C (QP_abbout, QP_mid);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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22 resistor_slot R295D (QM_abbout, QM_mid);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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23
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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24 /* capacitors in the middle */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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25 capacitor C295 (QM_mid, QP_mid);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 capacitor C296 (IM_mid, IP_mid);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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27
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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28 /* resistors joining with the bidirectional lines */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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29 resistor_slot R296A (IM_mid, IM_bidir);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 resistor_slot R296B (IP_mid, IP_bidir);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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31 resistor_slot R296C (QP_mid, QP_bidir);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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32 resistor_slot R296D (QM_mid, QM_bidir);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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33
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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34 endmodule