annotate venus/src/periph/calypso_uart_in.v @ 65:fb8fceab632c

venus/src/Makefile: unet-bind -c to check completeness
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 21:47:20 +0000
parents d33cb696b335
children
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1 /*
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2 * This module encapsulates the mobile power domain buffers
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3 * in front of Calypso UART inputs.
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4 */
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5
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6 module calypso_uart_in (GND, VBAT, Vio,
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7 Host_TxD, Host_RTS, Host_DTR, Host_TxD2,
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8 RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA);
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10 input GND, VBAT, Vio;
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11 input Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
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12 output RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA;
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14 /* U401 buffer common part */
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15 logic_ic_common U401_common (.Vcc(Vio), .GND(GND));
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17 /* bypass capacitor */
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18 capacitor U401_bypass (Vio, GND);
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20 /* buffer slots */
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21 buffer_slot_3state Host_TxD_buffer (.A(Host_TxD), .nOE(GND), .Y(RX_MODEM));
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22 buffer_slot_3state Host_RTS_buffer (.A(Host_RTS), .nOE(GND), .Y(CTS_MODEM));
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23 buffer_slot_3state Host_DTR_buffer (.A(Host_DTR), .nOE(GND), .Y(GPIO_DTR));
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24 buffer_slot_3state Host_TxD2_buffer (.A(Host_TxD2), .nOE(GND), .Y(RX_IRDA));
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26 /* pull-ups to VBAT */
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27 resistor Host_TxD_pullup (Host_TxD, VBAT);
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28 resistor Host_DTR_pullup (Host_DTR, VBAT);
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29 resistor Host_TxD2_pullup (Host_TxD2, VBAT);
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31 /* pull-down to GND */
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32 resistor Host_RTS_pulldown (Host_RTS, GND);
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34 endmodule