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annotate venus/src/periph/trrs_jack.v @ 81:fbe54d6cd082

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capture initial population of RLC67[0-5]
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Dec 2021 04:41:45 +0000
parents 3afd172b83e1
children
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1 /*
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2 * This Verilog module encapsulates the physical PCB footprint pinout
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3 * of the TRRS jack part we are using.
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4 */
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5
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6 module trrs_jack (T, R, R2, S, T_sw, R_sw);
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7
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8 inout T, R, R2, S;
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9 inout T_sw, R_sw;
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10
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11 pkg_TRRS_jack pkg (.pin_1(S),
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12 .pin_2(T),
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13 .pin_3(R),
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14 .pin_4(R2),
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15 .pin_5(T_sw),
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16 .pin_6(R_sw)
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17 );
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18
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19 endmodule