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minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents 3ed0f7a9c489
children
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9
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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1 /*
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2 * This module encapsulates the Rita chip along with the surrounding entourage
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3 * of power bypass capacitors; all other Rita signals are passed through
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4 * unchanged.
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5 */
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6
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7 module rita_wrap (GND, VBAT, VREG3, VRIO,
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8 XEN, XSEL, XIN, Clock_out_to_DBB,
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9 Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ,
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10 IN, IP, QN, QP,
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11 LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
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12 LBTXOUT, HBTXOUT,
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13 DAC, DET1, DET2, APC,
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14 RTEMP_VTEST);
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15
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16 input GND, VBAT, VRIO;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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17 output VREG3;
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18
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19 input XEN, XSEL, XIN;
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20 output Clock_out_to_DBB;
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21
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22 input Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ;
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23 inout IN, IP, QN, QP;
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24
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25 input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
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26 output LBTXOUT, HBTXOUT;
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27
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28 input DAC, DET1, DET2;
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29 output APC;
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30
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31 output RTEMP_VTEST;
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32
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33 /* Rita power nets contained inside this wrapper */
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34
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35 wire VREG1, VREG2;
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36 wire VCC4, VCC6, VCC9, VCC11;
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37 wire VBG;
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38
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39 /* instantiate the Rita! */
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40
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41 rita_rf_chip rita (.GND(GND),
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42 .CLK(Ctrl_CLK),
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43 .DATA(Ctrl_DATA),
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44 .STROBE(Ctrl_STROBE),
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45 .RESETZ(Ctrl_RESETZ),
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46 .IN(IN),
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47 .IP(IP),
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48 .QN(QN),
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49 .QP(QP),
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50 .LNAGSMN(LNAGSMN),
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51 .LNAGSMP(LNAGSMP),
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52 .LNADCSN(LNADCSN),
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53 .LNADCSP(LNADCSP),
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54 .LNAPCSN(LNAPCSN),
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55 .LNAPCSP(LNAPCSP),
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56 .LBTXOUT(LBTXOUT),
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57 .HBTXOUT(HBTXOUT),
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58 .DAC(DAC),
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59 .DET1(DET1),
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60 .DET2(DET2),
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61 .APC(APC),
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62 .RTEMP_VTEST(RTEMP_VTEST),
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63 .SIOUT_TST(), /* no connect */
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64 .TSTVCO1(), /* ditto */
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65 .TSTVCO2(), /* "" */
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66 .VBAT1(VBAT),
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67 .VBAT2(VBAT),
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68 .VREG1(VREG1),
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69 .VREG2(VREG2),
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70 .VREG3(VREG3),
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71 .VRIO(VRIO),
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72 .VCC1(VREG2),
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73 .VCC2(VREG2),
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74 .VCC3(VREG2),
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75 .VCC4(VCC4),
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76 .VCC5(VREG2),
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77 .VCC6(VCC6),
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78 .VCC7(VREG1),
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79 .VCC8(VREG3),
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80 .VCC9(VCC9),
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81 .VCC10(VREG3),
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82 .VCC11(VCC11),
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83 .VCC12(VREG1),
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84 .VCC13(VREG1),
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85 .VBG(VBG),
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86 .XEN(XEN),
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87 .XSEL(XSEL),
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88 .XIN(XIN),
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89 .XOUT(Clock_out_to_DBB)
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90 );
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91
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92 /* bypass caps on VREGn */
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93 capacitor C619 (VREG1, GND);
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94 capacitor C622 (VREG2, GND);
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95 capacitor C613 (VREG3, GND);
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96
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97 /* caps on VCCn */
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98
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99 /* VCC1 */ capacitor C629 (VREG2, GND);
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100 /* VCC2 */ capacitor C630 (VREG2, GND);
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101 /* VCC3 */ capacitor C631 (VREG2, GND);
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102 /* VCC4 */ capacitor C632 (VCC4, GND);
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103 /* VCC5 */ capacitor C633 (VREG2, GND);
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104 /* VCC6 */ capacitor C634 (VCC6, GND);
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105 /* VCC7 */ capacitor C620 (VREG1, GND);
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106 /* VCC8 */ capacitor C609 (VREG3, GND);
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107 /* VCC9 */ capacitor C608 (VCC9, GND);
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108 /* VCC10 */ capacitor C607 (VREG3, GND);
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109 /* VCC11 */ capacitor C606 (VCC11, GND);
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110 /* VCC12 */ capacitor C610 (VREG1, GND);
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111 /* VCC13 */ capacitor C617 (VREG1, GND);
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112
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113 capacitor C616 (VBG, GND);
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114
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115 capacitor XEN_cap (XEN, GND);
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116 capacitor XEN_cap2 (XEN, GND);
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117
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118 endmodule