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annotate venus/src/periph/Si9407AEY.v @ 98:3ab69117b09f default tip

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minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents 74a89c0a6466
children
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74a89c0a6466 Venus MCL: add Q401 charging circuit MOSFET
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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2 * This Verilog module encapsulates a MOSFET in a Si9407AEY-compatible
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3 * SOIC-8 footprint.
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4 */
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5
74a89c0a6466 Venus MCL: add Q401 charging circuit MOSFET
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6 module Si9407AEY (G, S, D);
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7
74a89c0a6466 Venus MCL: add Q401 charging circuit MOSFET
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8 input G, S;
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9 output D;
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10
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11 /* instantiate the package; the mapping of signals to pins is defined here */
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12
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13 pkg_IC_8pin pkg (.pin_1(S),
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14 .pin_2(S),
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15 .pin_3(S),
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16 .pin_4(G),
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17 .pin_5(D),
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18 .pin_6(D),
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19 .pin_7(D),
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20 .pin_8(D)
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21 );
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22
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23 endmodule