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annotate venus/src/periph/bl_current_select.v @ 98:3ab69117b09f default tip

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minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents 9f5a3567d699
children
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1 module bl_current_select (GND, Vio, BL_GPIO11, BL_GPIO12, SET);
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2
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3 input GND, Vio;
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4 input BL_GPIO11, BL_GPIO12;
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5 output SET;
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6
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7 wire buf_out_GPIO11, buf_out_GPIO12;
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8
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9 /* U403 buffer common part */
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10 logic_ic_common U403_common (.Vcc(Vio), .GND(GND));
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11
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12 /* bypass capacitor */
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13 capacitor U403_bypass (Vio, GND);
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15 /* buffer slots */
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16 buffer_slot_3state buf_GPIO11 (.A(Vio), .nOE(BL_GPIO11), .Y(buf_out_GPIO11));
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17 buffer_slot_3state buf_GPIO12 (.A(Vio), .nOE(BL_GPIO12), .Y(buf_out_GPIO12));
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18
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19 /* MAX1916 current control resistors */
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20 resistor R_fixed (Vio, SET);
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21 resistor R_GPIO11 (buf_out_GPIO11, SET);
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22 resistor R_GPIO12 (buf_out_GPIO12, SET);
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24 endmodule