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annotate venus/src/periph/lcd_subsystem.v @ 98:3ab69117b09f default tip

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minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents d55824058cfc
children
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1 module lcd_subsystem (GND, VBAT, Vio, DB, RD, WR, RS, CS, RESET,
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2 BL_GPIO9, BL_GPIO11, BL_GPIO12);
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3
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4 input GND, VBAT, Vio;
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5
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6 inout [15:0] DB;
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7 input RD, WR, RS, CS, RESET;
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8
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9 input BL_GPIO9, BL_GPIO11, BL_GPIO12;
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10
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11 wire [1:3] LEDK;
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12
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13 lcd_module lcd (.GND(GND),
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14 .VCI(Vio),
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15 .IOVCC(Vio),
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16 .DB(DB),
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17 .RD(RD),
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18 .WR(WR),
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19 .RS(RS),
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20 .CS(CS),
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21 .RESET(RESET),
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22 .IM0(GND),
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23 .LEDA(VBAT),
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24 /* LEDK broken out to allow reordering for layout */
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25 .LEDK[1](LEDK[1]),
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26 .LEDK[2](LEDK[2]),
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27 .LEDK[3](LEDK[3])
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28 );
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29
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30 capacitor LCD_bypass_cap (Vio, GND);
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31
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32 bl_current_sink bl (.GND(GND),
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33 .Vio(Vio),
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34 .BL_GPIO9(BL_GPIO9),
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35 .BL_GPIO11(BL_GPIO11),
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36 .BL_GPIO12(BL_GPIO12),
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37 /* LEDK broken out to allow reordering for layout */
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38 .LEDK[1](LEDK[1]),
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39 .LEDK[2](LEDK[2]),
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40 .LEDK[3](LEDK[3])
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41 );
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42
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43 endmodule