FreeCalypso > hg > freecalypso-schem2
annotate venus/src/usb/usb_domain.v @ 98:3ab69117b09f default tip
minnie/doc/Design-spec: finished in the first pass
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 01 Oct 2023 08:17:05 +0000 |
parents | 3becdb3b6dce |
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rev | line source |
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1 /* |
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2 * This module encapsulates the USB domain of FC Venus. |
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3 */ |
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4 |
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5 module usb_domain (GND, VBUS, Host_TxD, Host_RxD, Host_RTS, Host_CTS, |
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6 Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2, |
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7 RPWON, nTESTRESET); |
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8 |
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9 input GND; |
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10 output VBUS; |
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11 |
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12 output Host_TxD, Host_RTS, Host_DTR, Host_TxD2; |
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13 input Host_RxD, Host_CTS, Host_DCD, Host_RI, Host_RxD2; |
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14 output RPWON, nTESTRESET; |
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15 |
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16 /* USB domain wires */ |
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17 |
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18 wire P_5V, P_3V3; |
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19 |
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20 wire [7:0] ADBUS, BDBUS; |
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21 wire [3:0] ACBUS, BCBUS; |
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22 |
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23 usb_core usb ( .GND(GND), |
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24 .VBUS(VBUS), |
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25 .P_5V(P_5V), |
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26 .VCCIOA(P_3V3), |
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27 .VCCIOB(P_3V3), |
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28 .ADBUS(ADBUS), |
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29 .ACBUS(ACBUS), |
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30 .SI_WUA(P_3V3), |
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31 .BDBUS(BDBUS), |
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32 .BCBUS(BCBUS), |
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33 .SI_WUB(P_3V3), |
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34 .PWREN() /* no connect */ |
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35 ); |
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36 |
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37 regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3)); |
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38 |
39
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implement USB domain load resistor as proposed in document
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39 /* load resistor per USB-and-mobile-domains article section 2.4.1 */ |
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40 resistor Rload (P_3V3, GND); |
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41 |
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42 usb_domain_buf buf (.GND(GND), |
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43 .P_3V3(P_3V3), |
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44 .Int_TxD(ADBUS[0]), |
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45 .Int_RxD(ADBUS[1]), |
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46 .Int_RTS(ADBUS[2]), |
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47 .Int_CTS(ADBUS[3]), |
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48 .Int_DTR(ADBUS[4]), |
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49 .Int_DCD(ADBUS[6]), |
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50 .Int_RI(ADBUS[7]), |
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51 .Int_TxD2(BDBUS[0]), |
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52 .Int_RxD2(BDBUS[1]), |
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53 .Host_TxD(Host_TxD), |
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54 .Host_RxD(Host_RxD), |
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55 .Host_RTS(Host_RTS), |
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56 .Host_CTS(Host_CTS), |
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57 .Host_DTR(Host_DTR), |
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58 .Host_DCD(Host_DCD), |
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59 .Host_RI(Host_RI), |
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60 .Host_TxD2(Host_TxD2), |
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61 .Host_RxD2(Host_RxD2) |
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62 ); |
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63 |
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64 usb_domain_bctl bctl ( .GND(GND), |
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65 .P_3V3(P_3V3), |
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66 .ChanB_RTS(BDBUS[2]), |
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67 .ChanB_DTR(BDBUS[4]), |
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68 .CTL1_out(RPWON), |
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69 .CTL2_out(nTESTRESET) |
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70 ); |
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71 |
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72 endmodule |