annotate venus/src/usb/usb_domain_bctl.v @ 98:3ab69117b09f default tip

minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents 9309cebe07b8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
24
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This module encapsulates the USB domain circuit for boot control.
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 */
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 module usb_domain_bctl (GND, P_3V3, ChanB_RTS, ChanB_DTR, CTL1_out, CTL2_out);
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 input GND, P_3V3;
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 input ChanB_RTS, ChanB_DTR;
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 output CTL1_out, CTL2_out;
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 /* pull-up resistors on FT2232D outputs */
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 resistor ChanB_RTS_pullup (ChanB_RTS, P_3V3);
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 resistor ChanB_DTR_pullup (ChanB_DTR, P_3V3);
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 /* open drain buffers */
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 logic_ic_common od_buf_common ( .Vcc(P_3V3),
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 .GND(GND)
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 );
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 capacitor od_buf_bypass_cap (P_3V3, GND);
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23
40
9309cebe07b8 use buffer_slot_od primitive for slots of 74LVC2G07
Mychaela Falconia <falcon@freecalypso.org>
parents: 24
diff changeset
24 buffer_slot_od buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out));
9309cebe07b8 use buffer_slot_od primitive for slots of 74LVC2G07
Mychaela Falconia <falcon@freecalypso.org>
parents: 24
diff changeset
25 buffer_slot_od buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out));
24
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26
4722b265cb8c Venus src: USB domain captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 endmodule