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comparison venus/src/periph/audio_main.v @ 57:3afd172b83e1

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main audio channel implemented
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 02:22:39 +0000
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56:ec932276c8e6 57:3afd172b83e1
1 /*
2 * This Verilog module encapsulates our main audio channel.
3 */
4
5 module audio_main (GND, EARN, EARP, MICBIAS, MICIN, MICIP);
6
7 input GND;
8 input EARN, EARP;
9 input MICBIAS;
10 output MICIN, MICIP;
11
12 /* internal wires */
13
14 wire EARN_jack, EARP_jack, MIC_jack;
15
16 /* instantiate the jack */
17
18 trrs_jack jack (.T(EARP_jack),
19 .R(MIC_jack),
20 .R2(EARN_jack),
21 .S(GND),
22 .T_sw(), /* not used */
23 .R_sw() /* not used */
24 );
25
26 /* earpiece path filter caps */
27
28 capacitor C15 (EARP, EARN);
29 capacitor C16 (EARP, GND);
30 capacitor C17 (EARP, GND);
31 capacitor C18 (EARN, GND);
32 capacitor C19 (EARN, GND);
33
34 /* earpiece path filter inductors */
35
36 inductor L1 (EARP, EARP_jack);
37 inductor L2 (EARN, EARN_jack);
38
39 /* microphone input circuit */
40
41 capacitor C13 (MICBIAS, GND);
42
43 resistor R9 (MICBIAS, MIC_jack);
44 capacitor C14 (MIC_jack, GND);
45
46 capacitor C12 (MICBIAS, MICIP);
47 capacitor C21 (MIC_jack, MICIN);
48
49 capacitor C32 (MICIP, MICIN);
50
51 endmodule