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comparison venus/src/periph/trrs_jack.v @ 57:3afd172b83e1

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main audio channel implemented
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 02:22:39 +0000
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56:ec932276c8e6 57:3afd172b83e1
1 /*
2 * This Verilog module encapsulates the physical PCB footprint pinout
3 * of the TRRS jack part we are using.
4 */
5
6 module trrs_jack (T, R, R2, S, T_sw, R_sw);
7
8 inout T, R, R2, S;
9 inout T_sw, R_sw;
10
11 pkg_TRRS_jack pkg (.pin_1(S),
12 .pin_2(T),
13 .pin_3(R),
14 .pin_4(R2),
15 .pin_5(T_sw),
16 .pin_6(R_sw)
17 );
18
19 endmodule