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comparison venus/src/core/M034F.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 module M034F (ANT, GND, RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2,
2 TX_LOW, TX_HIGH, V_TX_LOW, V_TX_HIGH, V_RX_850);
3
4 inout ANT;
5 input GND;
6
7 output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2;
8 input TX_LOW, TX_HIGH;
9
10 input V_TX_LOW, V_TX_HIGH, V_RX_850;
11
12 /* instantiate the package; the mapping of signals to pins is defined here */
13
14 pkg_M034F pkg (.pin_1(ANT),
15 .pin_2(GND),
16 .pin_3(TX_HIGH),
17 .pin_4(GND),
18 .pin_5(GND),
19 .pin_6(TX_LOW),
20 .pin_7(V_TX_LOW),
21 .pin_8(V_TX_HIGH),
22 .pin_9(V_RX_850),
23 .pin_10(RX_DCS1),
24 .pin_11(RX_DCS2),
25 .pin_12(RX_PCS1),
26 .pin_13(RX_PCS2),
27 .pin_14(RX_LOW1),
28 .pin_15(RX_LOW2),
29 .pin_16(GND),
30 .pin_17(GND),
31 .pin_18(GND),
32 .pin_19(GND)
33 );
34
35 endmodule