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comparison venus/src/core/RF3166.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 module RF3166 (HB_RF_in, Band_Select, Tx_Enable, Vbatt, GND, Vramp, LB_RF_in,
2 LB_RF_out, HB_RF_out);
3
4 input LB_RF_in, HB_RF_in;
5 input Band_Select, Tx_Enable;
6 input GND, Vbatt, Vramp;
7 output LB_RF_out, HB_RF_out;
8
9 /* instantiate the package; the mapping of signals to pins is defined here */
10
11 pkg_RF3166 pkg (.pin_1(HB_RF_in),
12 .pin_2(Band_Select),
13 .pin_3(Tx_Enable),
14 .pin_4(Vbatt),
15 .pin_5(GND),
16 .pin_6(Vramp),
17 .pin_7(LB_RF_in),
18 .pin_8(LB_RF_out),
19 .pin_9(HB_RF_out),
20 .pin_10(GND),
21 .pin_11(GND),
22 .pin_12(GND),
23 .pin_13(GND),
24 .pin_14(GND),
25 .pin_15(GND),
26 .pin_16(GND),
27 .pin_17(GND),
28 .pin_18(GND),
29 .pin_19(GND),
30 .pin_20(GND),
31 .pin_21(GND),
32 .pin_22(GND),
33 .pin_23(GND),
34 .pin_24(GND),
35 .pin_25(GND),
36 .pin_26(GND),
37 .pin_27(GND),
38 .pin_28(GND),
39 .pin_29(GND),
40 .pin_30(GND),
41 .pin_31(GND)
42 );
43
44 endmodule