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comparison venus/src/core/S71PL064J.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 module S71PL064J (Flash_Vcc, RAM_Vcc, Vss,
2 A, DQ, OE, WE,
3 Flash_CE1, Flash_RST,
4 Flash_WP_ACC, Flash_ready_busy,
5 RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB);
6
7 input Flash_Vcc, RAM_Vcc, Vss;
8 input [21:0] A;
9 inout [15:0] DQ;
10 input OE, WE;
11 input Flash_CE1, Flash_RST, Flash_WP_ACC;
12 output Flash_ready_busy;
13 input RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB;
14
15 /* instantiate the package; the mapping of signals to balls is defined here */
16
17 pkg_TLC056 pkg (.A2(A[7]),
18 .A3(RAM_LB),
19 .A4(Flash_WP_ACC),
20 .A5(WE),
21 .A6(A[8]),
22 .A7(A[11]),
23 .B1(A[3]),
24 .B2(A[6]),
25 .B3(RAM_UB),
26 .B4(Flash_RST),
27 .B5(RAM_CE_acthigh),
28 .B6(A[19]),
29 .B7(A[12]),
30 .B8(A[15]),
31 .C1(A[2]),
32 .C2(A[5]),
33 .C3(A[18]),
34 .C4(Flash_ready_busy),
35 .C5(A[20]),
36 .C6(A[9]),
37 .C7(A[13]),
38 .C8(A[21]),
39 .D1(A[1]),
40 .D2(A[4]),
41 .D3(A[17]),
42 .D6(A[10]),
43 .D7(A[14]),
44 .D8(), /* no connect */
45 .E1(A[0]),
46 .E2(Vss),
47 .E3(DQ[1]),
48 .E6(DQ[6]),
49 .E7(), /* no connect */
50 .E8(A[16]),
51 .F1(Flash_CE1),
52 .F2(OE),
53 .F3(DQ[9]),
54 .F4(DQ[3]),
55 .F5(DQ[4]),
56 .F6(DQ[13]),
57 .F7(DQ[15]),
58 .F8(), /* no connect */
59 .G1(RAM_CE_actlow),
60 .G2(DQ[0]),
61 .G3(DQ[10]),
62 .G4(Flash_Vcc),
63 .G5(RAM_Vcc),
64 .G6(DQ[12]),
65 .G7(DQ[7]),
66 .G8(Vss),
67 .H2(DQ[8]),
68 .H3(DQ[2]),
69 .H4(DQ[11]),
70 .H5(), /* no connect */
71 .H6(DQ[5]),
72 .H7(DQ[14])
73 );
74
75 endmodule