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comparison venus/src/core/abb_block.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children c1256c8757c3
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8:d23dae52cd7b 9:3ed0f7a9c489
1 /*
2 * This module encapsulates the Iota ABB chip plus the following:
3 *
4 * - bypass capacitors on the VBAT input and the regulator outputs
5 * - all GND connections
6 * - IBIAS and VREF external components
7 * - UPR, VLMEM, VLRTC and everything connected to them
8 * - pull-up of SIM_IO to VSIM
9 * - cap on the AFC output
10 * - RC network joining BDL[IQ][MP] and BUL[IQ][MP]
11 * - VBACKUP resistor to GND in this FC Venus version
12 *
13 * All other Iota signals are passed through untouched.
14 */
15
16 module abb_block (GND, VBAT, VSIM, Vdbb, Vio, Vflash, Vsram, Vrtc,
17 nRESPWON, nTESTRESET,
18 Analog_IM, Analog_IP, Analog_QM, Analog_QP,
19 ADIN1, ADIN2, ADIN3, ADIN4, AFC, APC, AUXI, AUXON, AUXOP,
20 BDR, BDX, BFSR, BFSX, CK13M, CK32K, DAC, DBBSCK, DBBSIO,
21 DBBSRST, EARN, EARP,
22 HSMICBIAS, HSMICP, HSO, ICTL, INT1, INT2, ITWAKEUP,
23 LED_A, LED_B, LED_C, MICBIAS, MICIN, MICIP, ON_nOFF,
24 PCHG, PWON, RPWON,
25 TCK, TDI, TDO, TDR, TEN, TMS, UDR, UDX, UEN,
26 VBATS, VCCS, VCHG, VCK, VDR, VDX, VFS,
27 SIM_IO, SIM_CLK, SIM_RST);
28
29 input GND, VBAT;
30 output VSIM, Vdbb, Vio, Vflash, Vsram, Vrtc;
31
32 output nRESPWON;
33 input nTESTRESET;
34
35 inout Analog_IM, Analog_IP, Analog_QM, Analog_QP;
36
37 input ADIN1, ADIN2, ADIN3, ADIN4;
38 output AFC, APC, DAC;
39
40 input AUXI;
41 output AUXON, AUXOP;
42 output EARN, EARP;
43 output HSMICBIAS, HSO;
44 input HSMICP;
45 output MICBIAS;
46 input MICIN, MICIP;
47
48 input BDR, BFSR;
49 output BDX, BFSX;
50 input TDR, TEN;
51 input UDR, UEN;
52 output UDX;
53 output VCK, VDX, VFS;
54 input VDR;
55
56 input CK13M, CK32K, ITWAKEUP;
57 output INT1, INT2;
58 output ON_nOFF;
59
60 input DBBSCK, DBBSRST;
61 inout DBBSIO;
62
63 input PWON, RPWON;
64 output ICTL, PCHG;
65
66 output LED_A, LED_B, LED_C;
67
68 output SIM_CLK, SIM_RST;
69 inout SIM_IO;
70
71 input TCK, TDI, TMS;
72 output TDO;
73
74 input VBATS, VCCS, VCHG;
75
76 /* nets inside this module */
77 wire UPR, VLMEM, Vabb;
78 wire IBIAS, VREF;
79 wire BULIM, BULIP, BULQM, BULQP;
80 wire VBACKUP;
81
82 /* instantiate the Iota! */
83
84 iota_100ggm iota (.ADIN1(ADIN1),
85 .ADIN2(ADIN2),
86 .ADIN3(ADIN3),
87 .ADIN4(ADIN4),
88 .AFC(AFC),
89 .APC(APC),
90 .AUXI(AUXI),
91 .AUXON(AUXON),
92 .AUXOP(AUXOP),
93 .BDLIM(Analog_IM),
94 .BDLIP(Analog_IP),
95 .BDLQM(Analog_QM),
96 .BDLQP(Analog_QP),
97 .BDR(BDR),
98 .BDX(BDX),
99 .BFSR(BFSR),
100 .BFSX(BFSX),
101 .BULIM(BULIM),
102 .BULIP(BULIP),
103 .BULQM(BULQM),
104 .BULQP(BULQP),
105 .CK13M(CK13M),
106 .CK32K(CK32K),
107 .DAC(DAC),
108 .DBBSCK(DBBSCK),
109 .DBBSIO(DBBSIO),
110 .DBBSRST(DBBSRST),
111 .EARN(EARN),
112 .EARP(EARP),
113 .GNDA(GND),
114 .GNDAV(GND),
115 .GNDD(GND),
116 .GNDL1(GND),
117 .GNDL2(GND),
118 .HSMICBIAS(HSMICBIAS),
119 .HSMICP(HSMICP),
120 .HSO(HSO),
121 .IBIAS(IBIAS),
122 .ICTL(ICTL),
123 .INT1(INT1),
124 .INT2(INT2),
125 .ITWAKEUP(ITWAKEUP),
126 .LEDA(LED_A),
127 .LEDB1(LED_B),
128 .LEDB2(LED_B),
129 .LEDC(LED_C),
130 .MICBIAS(MICBIAS),
131 .MICIN(MICIN),
132 .MICIP(MICIP),
133 .ON_nOFF(ON_nOFF),
134 .PCHG(PCHG),
135 .PWON(PWON),
136 .REFGND(GND),
137 .RESPWONz(nRESPWON),
138 .RPWON(RPWON),
139 .SIMCK(SIM_CLK),
140 .SIMIO(SIM_IO),
141 .SIMRST(SIM_RST),
142 .TCK(TCK),
143 .TDI(TDI),
144 .TDO(TDO),
145 .TDR(TDR),
146 .TEN(TEN),
147 .TEST3(), /* no connect */
148 .TEST4(), /* ditto */
149 .TESTRSTz(nTESTRESET),
150 .TESTV(), /* no connect */
151 .TMS(TMS),
152 .UDR(UDR),
153 .UDX(UDX),
154 .UEN(UEN),
155 .UPR(UPR),
156 .VBACKUP(VBACKUP),
157 .VBAT(VBAT),
158 .VBATS(VBATS),
159 .VCABB(VBAT),
160 .VCCS(VCCS),
161 .VCDBB(VBAT),
162 .VCHG(VCHG),
163 .VCIO1(VBAT),
164 .VCIO2(VBAT),
165 .VCK(VCK),
166 .VCMEM(VBAT),
167 .VCRAM(VBAT),
168 .VDR(VDR),
169 .VDX(VDX),
170 .VFS(VFS),
171 .VLMEM(VLMEM),
172 .VLRTC(GND),
173 .VRABB(Vabb),
174 .VRDBB(Vdbb),
175 .VREF(VREF),
176 .VRIO1(Vio),
177 .VRIO2(Vio),
178 .VRMEM(Vflash),
179 .VRRAM(Vsram),
180 .VRRTC(Vrtc),
181 .VRSIM(VSIM),
182 .VSDBB(Vdbb),
183 .VXRTC() /* no connect */
184 );
185
186 /* power bypass caps per Leonardo schematics */
187
188 /* VBAT input */
189 capacitor C220 (VBAT, GND);
190 capacitor C221 (VBAT, GND);
191
192 /* regulator outputs */
193 capacitor C213 (Vabb, GND);
194 capacitor C214 (Vdbb, GND);
195 capacitor C215 (Vio, GND);
196 capacitor C216 (Vflash, GND);
197 capacitor C217 (Vsram, GND);
198 capacitor C218 (VSIM, GND);
199 capacitor C219 (Vrtc, GND);
200
201 /* UPR bypass cap */
202 capacitor C208 (UPR, GND);
203
204 /*
205 * VLMEM is pulled up to UPR, and we are eliminating the pull-down option
206 * on FC Venus - our LCD wiring is incompatible with 1.8V MEMIF.
207 */
208 resistor R209 (VLMEM, UPR);
209
210 /* nTESTRESET also needs to be pulled up to UPR */
211 resistor R208 (nTESTRESET, UPR);
212
213 /* IBIAS and VREF */
214 resistor R204 (IBIAS, GND);
215 capacitor C204 (VREF, GND);
216
217 /* pull-up on SIM_IO to VSIM */
218 resistor R206 (SIM_IO, VSIM);
219
220 /* cap on AFC output */
221 capacitor C205 (AFC, GND);
222
223 /* RC network joining BDL[IQ][MP] and BUL[IQ][MP] */
224
225 abb_rc_network abb_rc_network ( .IM_bidir(Analog_IM),
226 .IP_bidir(Analog_IP),
227 .QM_bidir(Analog_QM),
228 .QP_bidir(Analog_QP),
229 .IM_abbout(BULIM),
230 .IP_abbout(BULIP),
231 .QM_abbout(BULQM),
232 .QP_abbout(BULQP)
233 );
234
235 /* VBACKUP pull-down to GND */
236 resistor VBACKUP_pull_down (VBACKUP, GND);
237
238 endmodule