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comparison venus/src/core/baseband.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children 5ee03a306da3
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8:d23dae52cd7b 9:3ed0f7a9c489
1 /*
2 * This module encapsulates the DBB, the ABB and the connections between
3 * them. It approximately corresponds to the "200 - Baseband" sheet
4 * in the original Leonardo schematics.
5 */
6
7 module baseband (GND, VBAT, VSIM, Vio, Vflash, Vsram,
8 PWON, RPWON, nTESTRESET, ON_nOFF, CLKTCXO_IN,
9 TDI, TDO, TCK, TMS,
10 MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP,
11 MCU_nBLE, MCU_nBHE, MCU_nCS,
12 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
13 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
14 TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
15 MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
16 KBC, KBR, BU_PWT, LT_PWL,
17 GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT,
18 GPIO8, GPIO13,
19 ADIN1, ADIN2, ADIN3, ADIN4, DAC,
20 AUXI, AUXON, AUXOP, EARN, EARP, HSMICBIAS, HSMICP, HSO,
21 MICBIAS, MICIN, MICIP,
22 LED_A, LED_B, LED_C,
23 ICTL, PCHG, VBATS, VCCS, VCHG,
24 SIM_IO, SIM_CLK, SIM_RST,
25 Analog_IM, Analog_IP, Analog_QM, Analog_QP, AFC, APC,
26 TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita, TSPACT);
27
28 input GND, VBAT;
29 output VSIM, Vio, Vflash, Vsram;
30
31 input PWON, RPWON, nTESTRESET;
32 output ON_nOFF;
33
34 input CLKTCXO_IN;
35
36 input TDI, TCK, TMS;
37 output TDO;
38
39 output [22:0] MCU_A;
40 inout [15:0] MCU_D;
41 output MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP, MCU_nBLE, MCU_nBHE;
42 output [4:0] MCU_nCS;
43
44 output SCLK, SDO, nSCS1;
45 inout SDI_SDA, nSCS0_SCL;
46
47 output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
48 input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
49 inout DSR_LPG;
50
51 output MCSI_TXD;
52 input MCSI_RXD;
53 inout MCSI_CLK, MCSI_FSYNCH;
54
55 output [4:0] KBC;
56 input [4:0] KBR;
57 output BU_PWT, LT_PWL;
58
59 inout GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT, GPIO8, GPIO13;
60
61 input ADIN1, ADIN2, ADIN3, ADIN4;
62 output DAC;
63
64 input AUXI;
65 output AUXON, AUXOP;
66 output EARN, EARP;
67 output HSMICBIAS, HSO;
68 input HSMICP;
69 output MICBIAS;
70 input MICIN, MICIP;
71
72 output LED_A, LED_B, LED_C;
73
74 output ICTL, PCHG;
75 input VBATS, VCCS, VCHG;
76
77 output SIM_CLK, SIM_RST;
78 inout SIM_IO;
79
80 inout Analog_IM, Analog_IP, Analog_QM, Analog_QP;
81 output AFC, APC;
82 output TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita;
83 output [11:0] TSPACT;
84
85 /* nets between DBB and ABB */
86 wire Vdbb, Vrtc;
87 wire CLK13M_OUT, CLK32K_OUT, nRESPWON, IT_WAKEUP;
88 wire EXT_FIQ, EXT_IRQ;
89 wire TSPEN_Iota;
90
91 /* Baseband serial port */
92 wire BSP_dbb2abb_data, BSP_dbb2abb_sync;
93 wire BSP_abb2dbb_data, BSP_abb2dbb_sync;
94
95 /* Voiceband serial port */
96 wire VSP_DL_data, VSP_UL_data;
97 wire VSP_clock, VSP_sync;
98
99 /* MCU serial port */
100 wire USP_dbb2abb_data, USP_abb2dbb_data, USP_enable;
101
102 /* SIM interface at Vio */
103 wire DBBSIO, DBBSCLK, DBBSRST;
104
105 /* instantiate the DBB and ABB blocks! */
106
107 dbb_block dbb ( .GND(GND),
108 .Vdbb(Vdbb),
109 .Vio(Vio),
110 .Vflash(Vflash),
111 .Vrtc(Vrtc),
112 .TSPCLKX(TSPCLK),
113 .TSPDO(TSPDO),
114 .TSPDI_IO4(GPIO4),
115 .TSPEN[0](TSPEN_Iota),
116 .TSPEN[1](), /* no connect */
117 .TSPEN[2](TSPEN_Rita),
118 .TSPEN[3](), /* no connect */
119 .TSPACT(TSPACT),
120 .DATA(MCU_D),
121 .ADD(MCU_A),
122 .RnW(MCU_RnW),
123 .nFWE(MCU_nFWE),
124 .nFOE(MCU_nFOE),
125 .FDP(MCU_FDP),
126 .nBLE(MCU_nBLE),
127 .nBHE(MCU_nBHE),
128 .nCS(MCU_nCS),
129 .SCLK(SCLK),
130 .SDO(SDO),
131 .SDI_SDA(SDI_SDA),
132 .nSCS0_SCL(nSCS0_SCL),
133 .nSCS1(nSCS1),
134 .TX_IRDA(TX_IRDA),
135 .RX_IRDA(RX_IRDA),
136 .TXIR_IRDA(TXIR_IRDA),
137 .RXIR_IRDA(RXIR_IRDA),
138 .SD_IRDA(SD_IRDA),
139 .TX_MODEM(TX_MODEM),
140 .RX_MODEM(RX_MODEM),
141 .RTS_MODEM(RTS_MODEM),
142 .CTS_MODEM(CTS_MODEM),
143 .DSR_LPG(DSR_LPG),
144 .MCSI_TXD(MCSI_TXD),
145 .MCSI_RXD(MCSI_RXD),
146 .MCSI_CLK(MCSI_CLK),
147 .MCSI_FSYNCH(MCSI_FSYNCH),
148 .KBC(KBC),
149 .KBR(KBR),
150 .BU_PWT(BU_PWT),
151 .LT_PWL(LT_PWL),
152 .GPIO[0](GPIO0),
153 .GPIO[1](GPIO1),
154 .GPIO[2](GPIO2),
155 .GPIO[3](GPIO3),
156 .nRESET_OUT_IO7(GPIO7_RESETOUT),
157 .CLKTCXO(CLKTCXO_IN),
158 .CLK32K_OUT(CLK32K_OUT),
159 .CLK13M_OUT(CLK13M_OUT),
160 .nRESPWON(nRESPWON),
161 .EXT_FIQ(EXT_FIQ),
162 .EXT_IRQ(EXT_IRQ),
163 .TCXOEN(TCXOEN),
164 .RFEN(RFEN),
165 .ON_OFF(ON_nOFF),
166 .IT_WAKEUP(IT_WAKEUP),
167 .TDI(TDI),
168 .TDO(TDO),
169 .TCK(TCK),
170 .TMS(TMS),
171 .BFSR(BSP_abb2dbb_sync),
172 .BDR(BSP_abb2dbb_data),
173 .BFSX(BSP_dbb2abb_sync),
174 .BDX(BSP_dbb2abb_data),
175 .BCLKX_IO6(GPIO6),
176 .BCLKR_ARMCLK(GND),
177 .VDX(VSP_DL_data),
178 .VDR(VSP_UL_data),
179 .VFSRX(VSP_sync),
180 .VCLKRX(VSP_clock),
181 .MCUDI(USP_abb2dbb_data),
182 .MCUDO(USP_dbb2abb_data),
183 .MCUEN0(USP_enable),
184 .MCUEN1_IO8(GPIO8),
185 .MCUEN2_IO13(GPIO13),
186 .SIM_IO(DBBSIO),
187 .SIM_CLK(DBBSCLK),
188 .SIM_RST(DBBSRST)
189 );
190
191 abb_block abb ( .GND(GND),
192 .VBAT(VBAT),
193 .VSIM(VSIM),
194 .Vdbb(Vdbb),
195 .Vio(Vio),
196 .Vflash(Vflash),
197 .Vsram(Vsram),
198 .Vrtc(Vrtc),
199 .nRESPWON(nRESPWON),
200 .nTESTRESET(nTESTRESET),
201 .Analog_IM(Analog_IM),
202 .Analog_IP(Analog_IP),
203 .Analog_QM(Analog_QM),
204 .Analog_QP(Analog_QP),
205 .ADIN1(ADIN1),
206 .ADIN2(ADIN2),
207 .ADIN3(ADIN3),
208 .ADIN4(ADIN4),
209 .AFC(AFC),
210 .APC(APC),
211 .AUXI(AUXI),
212 .AUXON(AUXON),
213 .AUXOP(AUXOP),
214 .BDR(BSP_dbb2abb_data),
215 .BDX(BSP_abb2dbb_data),
216 .BFSR(BSP_dbb2abb_sync),
217 .BFSX(BSP_abb2dbb_sync),
218 .CK13M(CLK13M_OUT),
219 .CK32K(CLK32K_OUT),
220 .DAC(DAC),
221 .DBBSCK(DBBSCLK),
222 .DBBSIO(DBBSIO),
223 .DBBSRST(DBBSRST),
224 .EARN(EARN),
225 .EARP(EARP),
226 .HSMICBIAS(HSMICBIAS),
227 .HSMICP(HSMICP),
228 .HSO(HSO),
229 .ICTL(ICTL),
230 .INT1(EXT_FIQ),
231 .INT2(EXT_IRQ),
232 .ITWAKEUP(IT_WAKEUP),
233 .LED_A(LED_A),
234 .LED_B(LED_B),
235 .LED_C(LED_C),
236 .MICBIAS(MICBIAS),
237 .MICIN(MICIN),
238 .MICIP(MICIP),
239 .ON_nOFF(ON_nOFF),
240 .PCHG(PCHG),
241 .PWON(PWON),
242 .RPWON(RPWON),
243 .TCK(), /* no connect */
244 .TDI(), /* no connect */
245 .TDO(), /* no connect */
246 .TDR(TSPDO),
247 .TEN(TSPEN_Iota),
248 .TMS(), /* no connect */
249 .UDR(USP_dbb2abb_data),
250 .UDX(USP_abb2dbb_data),
251 .UEN(USP_enable),
252 .VBATS(VBATS),
253 .VCCS(VCCS),
254 .VCHG(VCHG),
255 .VCK(VSP_clock),
256 .VDR(VSP_DL_data),
257 .VDX(VSP_UL_data),
258 .VFS(VSP_sync),
259 .SIM_IO(SIM_IO),
260 .SIM_CLK(SIM_CLK),
261 .SIM_RST(SIM_RST)
262 );
263
264 /* there needs to be a pull-down resistor on the MCUDI/UDX net */
265 resistor R216 (USP_abb2dbb_data, GND);
266
267 endmodule