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comparison venus/src/core/clock_rf2dbb.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 module clock_rf2dbb (In, Out);
2
3 input In;
4 output Out;
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6 wire mid;
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8 resistor R251 (In, mid);
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10 capacitor C253 (mid, Out);
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12 endmodule