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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children 5ee03a306da3
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8:d23dae52cd7b 9:3ed0f7a9c489
1 /*
2 * This Verilog module encapsulates the Calypso chipset core part
3 * of our Venus development board.
4 */
5
6 module core (GND, VBAT1, VBAT2, VBAT3, VSIM, Vio,
7 PWON, RPWON, nTESTRESET, ON_nOFF,
8 TDI, TDO, TCK, TMS,
9 MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE,
10 EXT_nCS3, EXT_nCS4,
11 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
12 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
13 TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
14 MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
15 KBC, KBR, BU_PWT, LT_PWL,
16 GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT,
17 GPIO8, GPIO13,
18 ADIN1, ADIN2, ADIN3, DAC,
19 AUXI, AUXON, AUXOP, EARN, EARP, HSMICBIAS, HSMICP, HSO,
20 MICBIAS, MICIN, MICIP,
21 LED_A, LED_B, LED_C,
22 ICTL, PCHG, VBATS, VCCS, VCHG,
23 SIM_IO, SIM_CLK, SIM_RST, ANTENNA);
24
25 input GND, VBAT1, VBAT2, VBAT3;
26 output VSIM, Vio;
27
28 input PWON, RPWON, nTESTRESET;
29 output ON_nOFF;
30
31 input TDI, TCK, TMS;
32 output TDO;
33
34 output [22:0] MCU_A;
35 inout [15:0] MCU_D;
36 output MCU_RnW, MCU_nFWE, MCU_nFOE;
37 output EXT_nCS3, EXT_nCS4;
38
39 output SCLK, SDO, nSCS1;
40 inout SDI_SDA, nSCS0_SCL;
41
42 output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
43 input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
44 inout DSR_LPG;
45
46 output MCSI_TXD;
47 input MCSI_RXD;
48 inout MCSI_CLK, MCSI_FSYNCH;
49
50 output [4:0] KBC;
51 input [4:0] KBR;
52 output BU_PWT, LT_PWL;
53
54 inout GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO6, GPIO7_RESETOUT, GPIO8, GPIO13;
55
56 input ADIN1, ADIN2, ADIN3;
57 output DAC;
58
59 input AUXI;
60 output AUXON, AUXOP;
61 output EARN, EARP;
62 output HSMICBIAS, HSO;
63 input HSMICP;
64 output MICBIAS;
65 input MICIN, MICIP;
66
67 output LED_A, LED_B, LED_C;
68
69 output ICTL, PCHG;
70 input VBATS, VCCS, VCHG;
71
72 output SIM_CLK, SIM_RST;
73 inout SIM_IO;
74 inout ANTENNA;
75
76 /* wires between baseband and RF */
77 wire Clock_26MHz_RF_out, Clock_26MHz_DBB_in;
78 wire Analog_IM, Analog_IP, Analog_QM, Analog_QP;
79 wire AFC, APC;
80 wire TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita;
81 wire [11:0] TSPACT;
82 wire ADIN4;
83
84 /* wires between baseband and memory */
85 wire Vflash, Vsram;
86 wire MCU_FDP, MCU_nBLE, MCU_nBHE;
87 wire INT_nCS0, INT_nCS1, INT_nCS2;
88
89 /* instantiate the blocks! */
90
91 baseband bb (.GND(GND),
92 .VBAT(VBAT1),
93 .VSIM(VSIM),
94 .Vio(Vio),
95 .Vflash(Vflash),
96 .Vsram(Vsram),
97 .PWON(PWON),
98 .RPWON(RPWON),
99 .nTESTRESET(nTESTRESET),
100 .ON_nOFF(ON_nOFF),
101 .CLKTCXO_IN(Clock_26MHz_DBB_in),
102 .TDI(TDI),
103 .TDO(TDO),
104 .TCK(TCK),
105 .TMS(TMS),
106 .MCU_A(MCU_A),
107 .MCU_D(MCU_D),
108 .MCU_RnW(MCU_RnW),
109 .MCU_nFWE(MCU_nFWE),
110 .MCU_nFOE(MCU_nFOE),
111 .MCU_FDP(MCU_FDP),
112 .MCU_nBLE(MCU_nBLE),
113 .MCU_nBHE(MCU_nBHE),
114 .MCU_nCS[0](INT_nCS0),
115 .MCU_nCS[1](INT_nCS1),
116 .MCU_nCS[2](INT_nCS2),
117 .MCU_nCS[3](EXT_nCS3),
118 .MCU_nCS[4](EXT_nCS4),
119 .SCLK(SCLK),
120 .SDO(SDO),
121 .SDI_SDA(SDI_SDA),
122 .nSCS0_SCL(nSCS0_SCL),
123 .nSCS1(nSCS1),
124 .TX_IRDA(TX_IRDA),
125 .RX_IRDA(RX_IRDA),
126 .TXIR_IRDA(TXIR_IRDA),
127 .RXIR_IRDA(RXIR_IRDA),
128 .SD_IRDA(SD_IRDA),
129 .TX_MODEM(TX_MODEM),
130 .RX_MODEM(RX_MODEM),
131 .RTS_MODEM(RTS_MODEM),
132 .CTS_MODEM(CTS_MODEM),
133 .DSR_LPG(DSR_LPG),
134 .MCSI_TXD(MCSI_TXD),
135 .MCSI_RXD(MCSI_RXD),
136 .MCSI_CLK(MCSI_CLK),
137 .MCSI_FSYNCH(MCSI_FSYNCH),
138 .KBC(KBC),
139 .KBR(KBR),
140 .BU_PWT(BU_PWT),
141 .LT_PWL(LT_PWL),
142 .GPIO0(GPIO0),
143 .GPIO1(GPIO1),
144 .GPIO2(GPIO2),
145 .GPIO3(GPIO3),
146 .GPIO4(GPIO4),
147 .GPIO6(GPIO6),
148 .GPIO7_RESETOUT(GPIO7_RESETOUT),
149 .GPIO8(GPIO8),
150 .GPIO13(GPIO13),
151 .ADIN1(ADIN1),
152 .ADIN2(ADIN2),
153 .ADIN3(ADIN3),
154 .ADIN4(ADIN4),
155 .DAC(DAC),
156 .AUXI(AUXI),
157 .AUXON(AUXON),
158 .AUXOP(AUXOP),
159 .EARN(EARN),
160 .EARP(EARP),
161 .HSMICBIAS(HSMICBIAS),
162 .HSMICP(HSMICP),
163 .HSO(HSO),
164 .MICBIAS(MICBIAS),
165 .MICIN(MICIN),
166 .MICIP(MICIP),
167 .LED_A(LED_A),
168 .LED_B(LED_B),
169 .LED_C(LED_C),
170 .ICTL(ICTL),
171 .PCHG(PCHG),
172 .VBATS(VBATS),
173 .VCCS(VCCS),
174 .VCHG(VCHG),
175 .SIM_IO(SIM_IO),
176 .SIM_CLK(SIM_CLK),
177 .SIM_RST(SIM_RST),
178 .Analog_IM(Analog_IM),
179 .Analog_IP(Analog_IP),
180 .Analog_QM(Analog_QM),
181 .Analog_QP(Analog_QP),
182 .AFC(AFC),
183 .APC(APC),
184 .TCXOEN(TCXOEN),
185 .RFEN(RFEN),
186 .TSPCLK(TSPCLK),
187 .TSPDO(TSPDO),
188 .TSPEN_Rita(TSPEN_Rita),
189 .TSPACT(TSPACT)
190 );
191
192 memory mem (.GND(GND),
193 .Vflash(Vflash),
194 .Vsram(Vsram),
195 .MCU_A(MCU_A[22:1]),
196 .MCU_D(MCU_D[15:0]),
197 .MCU_nRD(MCU_nFOE),
198 .MCU_nWR(MCU_RnW),
199 .MCU_nBHE(MCU_nBHE),
200 .MCU_nBLE(MCU_nBLE),
201 .Flash_RST(MCU_FDP),
202 .CS_flash1(INT_nCS0),
203 .CS_RAM(INT_nCS1)
204 );
205
206 rf_section rf (.GND(GND),
207 .VBAT_REG(VBAT2),
208 .VBAT_PA(VBAT3),
209 .Vio(Vio),
210 .Analog_IM(Analog_IM),
211 .Analog_IP(Analog_IP),
212 .Analog_QM(Analog_QM),
213 .Analog_QP(Analog_QP),
214 .AFC(AFC),
215 .APC(APC),
216 .TCXOEN(TCXOEN),
217 .RFEN(RFEN),
218 .TSPCLK(TSPCLK),
219 .TSPDO(TSPDO),
220 .TSPEN_Rita(TSPEN_Rita),
221 .TSPACT(TSPACT),
222 .Clock_out_to_DBB(Clock_26MHz_RF_out),
223 .RTEMP_VTEST(ADIN4),
224 .ANTENNA(ANTENNA)
225 );
226
227 clock_rf2dbb clock_rf2dbb (.In(Clock_26MHz_RF_out),
228 .Out(Clock_26MHz_DBB_in)
229 );
230
231 endmodule