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comparison venus/src/core/dbb_block.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children 5ee03a306da3
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8:d23dae52cd7b 9:3ed0f7a9c489
1 /*
2 * This module encapsulates the Calypso DBB chip plus the following:
3 *
4 * - star points and bypass capacitors for the powering arrangement;
5 * - the 32 kHz xtal circuit with its special ground;
6 * - nIBOOT, IDDQ, SIM_CD and SIM_PWCTRL tie-offs;
7 * - nBSCAN and nEMU[1:0] no-connects.
8 *
9 * All other Calypso signals are passed through untouched.
10 */
11
12 module dbb_block (GND, Vdbb, Vio, Vflash, Vrtc,
13 TSPCLKX, TSPDO, TSPDI_IO4, TSPEN, TSPACT,
14 DATA, ADD, RnW, nFWE, nFOE, FDP, nBLE, nBHE, nCS,
15 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
16 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
17 TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
18 MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
19 KBC, KBR, BU_PWT, LT_PWL, GPIO,
20 nRESET_OUT_IO7, CLKTCXO,
21 CLK32K_OUT, CLK13M_OUT, nRESPWON, EXT_FIQ, EXT_IRQ,
22 TCXOEN, RFEN, ON_OFF, IT_WAKEUP,
23 TDI, TDO, TCK, TMS,
24 BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
25 VDX, VDR, VFSRX, VCLKRX,
26 MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
27 SIM_IO, SIM_CLK, SIM_RST);
28
29 input GND, Vdbb, Vio, Vflash, Vrtc;
30
31 output TSPCLKX, TSPDO;
32 inout TSPDI_IO4;
33 output [3:0] TSPEN;
34 output [11:0] TSPACT;
35
36 inout [15:0] DATA;
37 output [22:0] ADD;
38 output RnW, nFWE, nFOE, FDP, nBLE, nBHE;
39 output [4:0] nCS;
40
41 output SCLK, SDO, nSCS1;
42 inout SDI_SDA, nSCS0_SCL;
43
44 output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
45 input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
46 inout DSR_LPG;
47
48 output MCSI_TXD;
49 input MCSI_RXD;
50 inout MCSI_CLK, MCSI_FSYNCH;
51
52 output [4:0] KBC;
53 input [4:0] KBR;
54 output BU_PWT, LT_PWL;
55 inout [3:0] GPIO;
56
57 output nRESET_OUT_IO7;
58 input CLKTCXO;
59 output CLK32K_OUT, CLK13M_OUT;
60 input nRESPWON, EXT_FIQ, EXT_IRQ;
61
62 output TCXOEN, RFEN, IT_WAKEUP;
63 input ON_OFF;
64
65 input TDI, TCK, TMS;
66 output TDO;
67
68 input BFSR, BDR;
69 output BFSX, BDX;
70 inout BCLKX_IO6;
71 input BCLKR_ARMCLK;
72
73 output VDX;
74 input VDR, VFSRX, VCLKRX;
75
76 input MCUDI;
77 output MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13;
78
79 inout SIM_IO;
80 output SIM_CLK, SIM_RST;
81
82 /* nets inside this module */
83 wire SIM_PWCTRL;
84 wire GND_32khz, OSC32K_IN, OSC32K_OUT, OSC32K_OUT_2;
85 wire VDD_PLL, VDD_CORE;
86
87 starpoint HST201 (Vdbb, VDD_PLL);
88 starpoint HST202 (Vdbb, VDD_CORE);
89
90 /* instantiate the Calypso! */
91
92 calypso_179ghh calypso (.TSPCLKX(TSPCLKX),
93 .TSPDO(TSPDO),
94 .TSPDI_IO4(TSPDI_IO4),
95 .TSPEN(TSPEN),
96 .TSPACT(TSPACT),
97 .DATA(DATA),
98 .ADD(ADD),
99 .RnW(RnW),
100 .nFWE(nFWE),
101 .nFOE(nFOE),
102 .FDP(FDP),
103 .nBLE(nBLE),
104 .nBHE(nBHE),
105 .nCS(nCS),
106 .VDDS_MIF(Vflash),
107 .VDDS_1(Vio),
108 .VDDS_2(Vio),
109 .VDD(VDD_CORE),
110 .VSS(GND),
111 .VDDS_RTC(Vrtc),
112 .VDD_RTC(Vrtc),
113 .VSS_RTC(GND),
114 .VDD_ANG(Vio),
115 .VSS_ANG(GND),
116 .VDD_PLL(VDD_PLL),
117 .VSS_PLL(GND),
118 .SCLK(SCLK),
119 .SDO(SDO),
120 .SDI_SDA(SDI_SDA),
121 .nSCS0_SCL(nSCS0_SCL),
122 .nSCS1(nSCS1),
123 .TX_IRDA(TX_IRDA),
124 .RX_IRDA(RX_IRDA),
125 .TXIR_IRDA(TXIR_IRDA),
126 .RXIR_IRDA(RXIR_IRDA),
127 .SD_IRDA(SD_IRDA),
128 .TX_MODEM(TX_MODEM),
129 .RX_MODEM(RX_MODEM),
130 .RTS_MODEM(RTS_MODEM),
131 .CTS_MODEM(CTS_MODEM),
132 .DSR_LPG(DSR_LPG),
133 .MCSI_TXD(MCSI_TXD),
134 .MCSI_RXD(MCSI_RXD),
135 .MCSI_CLK(MCSI_CLK),
136 .MCSI_FSYNCH(MCSI_FSYNCH),
137 .KBC(KBC),
138 .KBR(KBR),
139 .BU_PWT(BU_PWT),
140 .LT_PWL(LT_PWL),
141 .GPIO(GPIO),
142 .nRESET_OUT_IO7(nRESET_OUT_IO7),
143 .nIBOOT(GND),
144 .IDDQ(GND),
145 .CLKTCXO(CLKTCXO),
146 .VSSO(GND_32khz),
147 .OSC32K_IN(OSC32K_IN),
148 .OSC32K_OUT(OSC32K_OUT),
149 .CLK32K_OUT(CLK32K_OUT),
150 .CLK13M_OUT(CLK13M_OUT),
151 .nRESPWON(nRESPWON),
152 .EXT_FIQ(EXT_FIQ),
153 .EXT_IRQ(EXT_IRQ),
154 .TCXOEN(TCXOEN),
155 .RFEN(RFEN),
156 .ON_OFF(ON_OFF),
157 .IT_WAKEUP(IT_WAKEUP),
158 .nEMU(), /* no connect */
159 .nBSCAN(), /* ditto */
160 .TDI(TDI),
161 .TDO(TDO),
162 .TCK(TCK),
163 .TMS(TMS),
164 .BFSR(BFSR),
165 .BDR(BDR),
166 .BFSX(BFSX),
167 .BDX(BDX),
168 .BCLKX_IO6(BCLKX_IO6),
169 .BCLKR_ARMCLK(BCLKR_ARMCLK),
170 .VDX(VDX),
171 .VDR(VDR),
172 .VFSRX(VFSRX),
173 .VCLKRX(VCLKRX),
174 .MCUDI(MCUDI),
175 .MCUDO(MCUDO),
176 .MCUEN0(MCUEN0),
177 .MCUEN1_IO8(MCUEN1_IO8),
178 .MCUEN2_IO13(MCUEN2_IO13),
179 .SIM_IO(SIM_IO),
180 .SIM_CLK(SIM_CLK),
181 .SIM_RST(SIM_RST),
182 .SIM_CD(Vio),
183 .SIM_PWCTRL_IO5(SIM_PWCTRL));
184
185 /* power bypass caps, absolutely unchanged from Leonardo */
186
187 capacitor C209 (Vflash, GND);
188 capacitor C210 (Vio, GND);
189 capacitor C211 (VDD_CORE, GND);
190 capacitor C212 (VDD_PLL, GND);
191
192 /* 32.768 kHz xtal circuit, following Leonardo schematics */
193
194 /* special ground */
195 starpoint HST203 (GND, GND_32khz);
196
197 /* resistor and extra cap on OSC32K_OUT */
198 resistor R215 (OSC32K_OUT, OSC32K_OUT_2);
199 capacitor C223 (OSC32K_OUT, GND); /* regular GND per Leonardo schem */
200
201 /* actual xtal and caps */
202 xtal_32khz_wrap xtal (OSC32K_IN, OSC32K_OUT_2, GND); /* pkg case GND */
203 capacitor C202 (OSC32K_IN, GND_32khz);
204 capacitor C203 (OSC32K_OUT_2, GND_32khz);
205
206 /* Vrtc bypass cap */
207 capacitor C201 (Vrtc, GND_32khz);
208
209 /* SIM_PWCTRL resistor like on Leonardo schematics */
210 resistor R207 (SIM_PWCTRL, SIM_IO);
211
212 endmodule