FreeCalypso > hg > freecalypso-schem2

comparison venus/src/core/iota_100ggm.v @ 9:3ed0f7a9c489

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children
comparison
equal deleted inserted replaced
8:d23dae52cd7b 9:3ed0f7a9c489
1 module iota_100ggm (ADIN1, ADIN2, ADIN3, ADIN4, AFC, APC, AUXI, AUXON, AUXOP,
2 BDLIM, BDLIP, BDLQM, BDLQP, BDR, BDX, BFSR, BFSX, BULIM,
3 BULIP, BULQM, BULQP, CK13M, CK32K, DAC, DBBSCK, DBBSIO,
4 DBBSRST, EARN, EARP, GNDA, GNDAV, GNDD, GNDL1, GNDL2,
5 HSMICBIAS, HSMICP, HSO, IBIAS, ICTL, INT1, INT2, ITWAKEUP,
6 LEDA, LEDB1, LEDB2, LEDC, MICBIAS, MICIN, MICIP, ON_nOFF,
7 PCHG, PWON, REFGND, RESPWONz, RPWON, SIMCK, SIMIO, SIMRST,
8 TCK, TDI, TDO, TDR, TEN, TEST3, TEST4, TESTRSTz, TESTV,
9 TMS, UDR, UDX, UEN, UPR, VBACKUP, VBAT, VBATS, VCABB, VCCS,
10 VCDBB, VCHG, VCIO1, VCIO2, VCK, VCMEM, VCRAM, VDR, VDX,
11 VFS, VLMEM, VLRTC, VRABB, VRDBB, VREF, VRIO1, VRIO2, VRMEM,
12 VRRAM, VRRTC, VRSIM, VSDBB, VXRTC);
13
14 input ADIN1, ADIN2, ADIN3, ADIN4;
15 output AFC, APC, DAC;
16
17 input AUXI;
18 output AUXON, AUXOP;
19 output EARN, EARP;
20 output HSMICBIAS, HSO;
21 input HSMICP;
22 output MICBIAS;
23 input MICIN, MICIP;
24
25 input BDLIM, BDLIP, BDLQM, BDLQP;
26 output BULIM, BULIP, BULQM, BULQP;
27
28 input BDR, BFSR;
29 output BDX, BFSX;
30 input TDR, TEN;
31 input UDR, UEN;
32 output UDX;
33 output VCK, VDX, VFS;
34 input VDR;
35
36 input CK13M, CK32K, ITWAKEUP;
37 output INT1, INT2;
38 output ON_nOFF, RESPWONz;
39
40 input DBBSCK, DBBSRST;
41 inout DBBSIO;
42
43 input GNDA, GNDAV, GNDD, GNDL1, GNDL2;
44
45 inout IBIAS, VREF, REFGND;
46
47 input PWON, RPWON;
48 output ICTL, PCHG;
49
50 output LEDA, LEDB1, LEDB2, LEDC;
51
52 output SIMCK, SIMRST;
53 inout SIMIO;
54
55 input TCK, TDI, TMS;
56 output TDO;
57 inout TEST3, TEST4;
58 input TESTRSTz;
59 output TESTV;
60
61 inout UPR;
62 input VBACKUP, VBAT, VBATS, VCABB, VCCS, VCDBB, VCHG, VCIO1, VCIO2;
63 input VCMEM, VCRAM;
64
65 input VLMEM, VLRTC;
66 output VRABB, VRDBB, VRIO1, VRIO2, VRMEM, VRRAM, VRRTC, VRSIM;
67
68 input VSDBB;
69 inout VXRTC;
70
71 /* instantiate the package; the mapping of signals to balls is defined here */
72
73 pkg_100GGM pkg (.B6(ADIN1),
74 .A6(ADIN2),
75 .C7(ADIN3),
76 .C6(ADIN4),
77 .J4(AFC),
78 .K4(APC),
79 .G7(AUXI),
80 .K10(AUXON),
81 .K9(AUXOP),
82 .F10(BDLIM),
83 .F9(BDLIP),
84 .E9(BDLQM),
85 .E10(BDLQP),
86 .J3(BDR),
87 .J2(BDX),
88 .H3(BFSR),
89 .K2(BFSX),
90 .D10(BULIM),
91 .D9(BULIP),
92 .C9(BULQM),
93 .C10(BULQP),
94 .E4(CK13M),
95 .E2(CK32K),
96 .H4(DAC),
97 .F4(DBBSCK),
98 .E5(DBBSIO),
99 .G4(DBBSRST),
100 .J10(EARN),
101 .J9(EARP),
102 .G10(GNDA),
103 .G6(GNDAV),
104 .A3(GNDD),
105 .B9(GNDL1),
106 .A9(GNDL2),
107 .K8(HSMICBIAS),
108 .K7(HSMICP),
109 .H9(HSO),
110 .B7(IBIAS),
111 .D6(ICTL),
112 .H6(INT1),
113 .E6(INT2),
114 .D2(ITWAKEUP),
115 .B8(LEDA),
116 .B10(LEDB1),
117 .A10(LEDB2),
118 .C8(LEDC),
119 .J8(MICBIAS),
120 .H7(MICIN),
121 .J7(MICIP),
122 .E3(ON_nOFF),
123 .B5(PCHG),
124 .F8(PWON),
125 .A7(REFGND),
126 .D3(RESPWONz),
127 .F7(RPWON),
128 .C4(SIMCK),
129 .B3(SIMIO),
130 .D4(SIMRST),
131 .D8(TCK),
132 .D7(TDI),
133 .E7(TDO),
134 .G3(TDR),
135 .H1(TEN),
136 .J6(TEST3),
137 .F6(TEST4),
138 .H8(TESTRSTz),
139 .G8(TESTV),
140 .E8(TMS),
141 .K5(UDR),
142 .J5(UDX),
143 .K6(UEN),
144 .C2(UPR),
145 .E1(VBACKUP),
146 .A4(VBAT),
147 .C5(VBATS),
148 .G9(VCABB),
149 .D5(VCCS),
150 .K1(VCDBB),
151 .A5(VCHG),
152 .A2(VCIO1),
153 .A1(VCIO2),
154 .K3(VCK),
155 .G2(VCMEM),
156 .F2(VCRAM),
157 .F5(VDR),
158 .H5(VDX),
159 .G5(VFS),
160 .F3(VLMEM),
161 .C3(VLRTC),
162 .H10(VRABB),
163 .J1(VRDBB),
164 .A8(VREF),
165 .B2(VRIO1),
166 .B1(VRIO2),
167 .G1(VRMEM),
168 .F1(VRRAM),
169 .D1(VRRTC),
170 .B4(VRSIM),
171 .H2(VSDBB),
172 .C1(VXRTC)
173 );
174
175 endmodule