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comparison venus/src/core/rf_pa_block.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 /*
2 * This module encapsulates the RF PA along with its power bypass caps
3 * and the Rs and Cs on the control inputs.
4 */
5
6 module rf_pa_block (GND, VBAT, Band_Select, Tx_Enable, APC_in,
7 LB_RF_in, HB_RF_in, LB_RF_out, HB_RF_out);
8
9 input GND, VBAT;
10 input Band_Select, Tx_Enable, APC_in;
11 input LB_RF_in, HB_RF_in;
12 output LB_RF_out, HB_RF_out;
13
14 /*
15 * A little bit of muck with the control inputs, following Leonardo
16 * and Openmoko schematics. On FC Venus we completely eliminate
17 * R621 and R622.
18 */
19
20 wire APC_after_resistor;
21
22 resistor R623 (APC_in, APC_after_resistor);
23 capacitor C648 (APC_after_resistor, GND);
24 capacitor C656 (Band_Select, GND);
25
26 /* instantiate the PA itself */
27
28 RF3166 PA (.HB_RF_in(HB_RF_in),
29 .Band_Select(Band_Select),
30 .Tx_Enable(Tx_Enable),
31 .Vbatt(VBAT),
32 .GND(GND),
33 .Vramp(APC_after_resistor),
34 .LB_RF_in(LB_RF_in),
35 .LB_RF_out(LB_RF_out),
36 .HB_RF_out(HB_RF_out)
37 );
38
39 /* 4 bypass caps per both Leonardo and Openmoko schematics */
40
41 capacitor C651 (VBAT, GND);
42 capacitor C652 (VBAT, GND);
43 capacitor C653 (VBAT, GND);
44 capacitor C654 (VBAT, GND);
45
46 endmodule