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comparison venus/src/core/rita_rf_chip.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 module rita_rf_chip (GND,
2 CLK, DATA, STROBE, RESETZ,
3 IN, IP, QN, QP,
4 LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
5 LBTXOUT, HBTXOUT,
6 DAC, DET1, DET2, APC,
7 RTEMP_VTEST, SIOUT_TST, TSTVCO1, TSTVCO2,
8 VBAT1, VBAT2, VREG1, VREG2, VREG3, VRIO,
9 VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9,
10 VCC10, VCC11, VCC12, VCC13, VBG,
11 XEN, XSEL, XIN, XOUT);
12
13 input GND;
14 input CLK, DATA, STROBE, RESETZ;
15 inout IN, IP, QN, QP;
16
17 input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
18 output LBTXOUT, HBTXOUT;
19
20 input DAC, DET1, DET2;
21 output APC;
22
23 output RTEMP_VTEST, SIOUT_TST, TSTVCO1, TSTVCO2;
24
25 input VBAT1, VBAT2, VRIO;
26 output VREG1, VREG2, VREG3;
27 inout VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9;
28 inout VCC10, VCC11, VCC12, VCC13, VBG;
29
30 input XEN, XSEL;
31 inout XIN;
32 output XOUT;
33
34 /* instantiate the package; the mapping of signals to pins is defined here */
35
36 pkg_Rita_RF pkg (.pin_1(XSEL),
37 .pin_2(XEN),
38 .pin_3(RESETZ),
39 .pin_4(VCC1),
40 .pin_5(DATA),
41 .pin_6(VCC2),
42 .pin_7(CLK),
43 .pin_8(VCC3),
44 .pin_9(STROBE),
45 .pin_10(VCC4),
46 .pin_11(VCC5),
47 .pin_12(VCC6),
48 .pin_13(SIOUT_TST),
49 .pin_14(RTEMP_VTEST),
50 .pin_15(LNAPCSP),
51 .pin_16(LNAPCSN),
52 .pin_17(VCC7),
53 .pin_18(LNADCSP),
54 .pin_19(LNADCSN),
55 .pin_20(VBG),
56 .pin_21(LNAGSMP),
57 .pin_22(LNAGSMN),
58 .pin_23(VREG3),
59 .pin_24(VBAT2),
60 .pin_25(DET1),
61 .pin_26(DET2),
62 .pin_27(APC),
63 .pin_28(DAC),
64 .pin_29(HBTXOUT),
65 .pin_30(VCC8),
66 .pin_31(LBTXOUT),
67 .pin_32(VCC9),
68 .pin_33(VCC10),
69 .pin_34(TSTVCO1),
70 .pin_35(TSTVCO2),
71 .pin_36(VCC11),
72 .pin_37(VCC12),
73 .pin_38(IN),
74 .pin_39(IP),
75 .pin_40(QP),
76 .pin_41(QN),
77 .pin_42(VCC13),
78 .pin_43(VREG1),
79 .pin_44(VBAT1),
80 .pin_45(VREG2),
81 .pin_46(VRIO),
82 .pin_47(XOUT),
83 .pin_48(XIN),
84 .pin_49(GND)
85 );
86
87 endmodule