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comparison venus/src/core/rita_wrap.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 /*
2 * This module encapsulates the Rita chip along with the surrounding entourage
3 * of power bypass capacitors; all other Rita signals are passed through
4 * unchanged.
5 */
6
7 module rita_wrap (GND, VBAT, VREG3, VRIO,
8 XEN, XSEL, XIN, Clock_out_to_DBB,
9 Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ,
10 IN, IP, QN, QP,
11 LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
12 LBTXOUT, HBTXOUT,
13 DAC, DET1, DET2, APC,
14 RTEMP_VTEST);
15
16 input GND, VBAT, VRIO;
17 output VREG3;
18
19 input XEN, XSEL, XIN;
20 output Clock_out_to_DBB;
21
22 input Ctrl_CLK, Ctrl_DATA, Ctrl_STROBE, Ctrl_RESETZ;
23 inout IN, IP, QN, QP;
24
25 input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
26 output LBTXOUT, HBTXOUT;
27
28 input DAC, DET1, DET2;
29 output APC;
30
31 output RTEMP_VTEST;
32
33 /* Rita power nets contained inside this wrapper */
34
35 wire VREG1, VREG2;
36 wire VCC4, VCC6, VCC9, VCC11;
37 wire VBG;
38
39 /* instantiate the Rita! */
40
41 rita_rf_chip rita (.GND(GND),
42 .CLK(Ctrl_CLK),
43 .DATA(Ctrl_DATA),
44 .STROBE(Ctrl_STROBE),
45 .RESETZ(Ctrl_RESETZ),
46 .IN(IN),
47 .IP(IP),
48 .QN(QN),
49 .QP(QP),
50 .LNAGSMN(LNAGSMN),
51 .LNAGSMP(LNAGSMP),
52 .LNADCSN(LNADCSN),
53 .LNADCSP(LNADCSP),
54 .LNAPCSN(LNAPCSN),
55 .LNAPCSP(LNAPCSP),
56 .LBTXOUT(LBTXOUT),
57 .HBTXOUT(HBTXOUT),
58 .DAC(DAC),
59 .DET1(DET1),
60 .DET2(DET2),
61 .APC(APC),
62 .RTEMP_VTEST(RTEMP_VTEST),
63 .SIOUT_TST(), /* no connect */
64 .TSTVCO1(), /* ditto */
65 .TSTVCO2(), /* "" */
66 .VBAT1(VBAT),
67 .VBAT2(VBAT),
68 .VREG1(VREG1),
69 .VREG2(VREG2),
70 .VREG3(VREG3),
71 .VRIO(VRIO),
72 .VCC1(VREG2),
73 .VCC2(VREG2),
74 .VCC3(VREG2),
75 .VCC4(VCC4),
76 .VCC5(VREG2),
77 .VCC6(VCC6),
78 .VCC7(VREG1),
79 .VCC8(VREG3),
80 .VCC9(VCC9),
81 .VCC10(VREG3),
82 .VCC11(VCC11),
83 .VCC12(VREG1),
84 .VCC13(VREG1),
85 .VBG(VBG),
86 .XEN(XEN),
87 .XSEL(XSEL),
88 .XIN(XIN),
89 .XOUT(Clock_out_to_DBB)
90 );
91
92 /* bypass caps on VREGn */
93 capacitor C619 (VREG1, GND);
94 capacitor C622 (VREG2, GND);
95 capacitor C613 (VREG3, GND);
96
97 /* caps on VCCn */
98
99 /* VCC1 */ capacitor C629 (VREG2, GND);
100 /* VCC2 */ capacitor C630 (VREG2, GND);
101 /* VCC3 */ capacitor C631 (VREG2, GND);
102 /* VCC4 */ capacitor C632 (VCC4, GND);
103 /* VCC5 */ capacitor C633 (VREG2, GND);
104 /* VCC6 */ capacitor C634 (VCC6, GND);
105 /* VCC7 */ capacitor C620 (VREG1, GND);
106 /* VCC8 */ capacitor C609 (VREG3, GND);
107 /* VCC9 */ capacitor C608 (VCC9, GND);
108 /* VCC10 */ capacitor C607 (VREG3, GND);
109 /* VCC11 */ capacitor C606 (VCC11, GND);
110 /* VCC12 */ capacitor C610 (VREG1, GND);
111 /* VCC13 */ capacitor C617 (VREG1, GND);
112
113 capacitor C616 (VBG, GND);
114
115 capacitor XEN_cap (XEN, GND);
116 capacitor XEN_cap2 (XEN, GND);
117
118 endmodule