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comparison venus/src/top/board.v @ 26:4baae6215619

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Venus: reached the point of compiling sverp.unet
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 20 Nov 2021 21:54:27 +0000
parents
children 541b55e6bf47
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25:250fd753c0c5 26:4baae6215619
1 /*
2 * This structural Verilog module is the top level for FC Venus board.
3 * It interconnects the two principal domains: mobile and USB.
4 */
5
6 module board ();
7
8 wire GND, VBUS, VCHG;
9
10 wire Host_TxD, Host_RxD, Host_RTS, Host_CTS;
11 wire Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2;
12
13 wire RPWON, nTESTRESET;
14
15 /* mobile and USB domains */
16
17 mobile mob (.GND(GND),
18 .VCHG(VCHG),
19 .Host_TxD(Host_TxD),
20 .Host_RxD(Host_RxD),
21 .Host_RTS(Host_RTS),
22 .Host_CTS(Host_CTS),
23 .Host_DTR(Host_DTR),
24 .Host_DCD(Host_DCD),
25 .Host_RI(Host_RI),
26 .Host_TxD2(Host_TxD2),
27 .Host_RxD2(Host_RxD2),
28 .RPWON(RPWON),
29 .nTESTRESET(nTESTRESET)
30 );
31
32 usb_domain usb (.GND(GND),
33 .VBUS(VBUS),
34 .Host_TxD(Host_TxD),
35 .Host_RxD(Host_RxD),
36 .Host_RTS(Host_RTS),
37 .Host_CTS(Host_CTS),
38 .Host_DTR(Host_DTR),
39 .Host_DCD(Host_DCD),
40 .Host_RI(Host_RI),
41 .Host_TxD2(Host_TxD2),
42 .Host_RxD2(Host_RxD2),
43 .RPWON(RPWON),
44 .nTESTRESET(nTESTRESET)
45 );
46
47 /* charging control switch */
48
49 switch_2pin chg_switch (VBUS, VCHG);
50
51 /* pull-down resistors before and after the switch */
52
53 resistor VBUS_pulldown (VBUS, GND);
54 resistor VCHG_pulldown (VCHG, GND);
55
56 endmodule