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comparison venus/src/periph/sim_socket_block.v @ 17:5b18183f55bf

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Venus src: SIM socket block captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 20:59:14 +0000
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children d33cb696b335
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16:3d5c40988a6b 17:5b18183f55bf
1 /*
2 * This module encapsulates the complete SIM socket block:
3 * the actual socket, the bypass cap and our SIM_CD circuit.
4 */
5
6 module sim_socket_block (GND, Vio, VSIM, SIM_CLK, SIM_RST, SIM_IO, SIM_CD);
7
8 input GND, Vio, VSIM;
9 input SIM_CLK, SIM_RST;
10 inout SIM_IO;
11 output SIM_CD;
12
13 wire SIM_CD_inverted;
14
15 sim_socket_wrap socket (.C1(VSIM),
16 .C2(SIM_RST),
17 .C3(SIM_CLK),
18 .C5(GND),
19 .C6(VSIM),
20 .C7(SIM_IO),
21 .SW1(GND),
22 .SW2(SIM_CD_inverted)
23 );
24
25 /* cap per Leonardo schematics */
26 capacitor C306 (VSIM, GND);
27
28 /* pull-up on the switch line */
29 resistor switch_pullup (SIM_CD_inverted, Vio);
30
31 /* inverting buffer for SIM_CD */
32 inv_buffer_74LVC1G04 inv (.GND(GND),
33 .Vcc(Vio),
34 .A(SIM_CD_inverted),
35 .Y(SIM_CD)
36 );
37
38 endmodule