FreeCalypso > hg > freecalypso-schem2
comparison venus/src/primitives @ 6:64ce89bd3376
Venus primitives file started
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Fri, 19 Nov 2021 03:07:48 +0000 |
parents | |
children | d23dae52cd7b |
comparison
equal
deleted
inserted
replaced
5:e449bb0779c4 | 6:64ce89bd3376 |
---|---|
1 /* | |
2 * This file defines the primitives to be instantiated from the structural | |
3 * Verilog source for the board: IC package types, basic components and | |
4 * subpackages to be mapped later in the MCL binding step. | |
5 */ | |
6 | |
7 resistor numpins 2; | |
8 capacitor numpins 2; | |
9 inductor numpins 2; | |
10 rlc_generic numpins 2; /* "any" RLC for matching network topologies */ | |
11 starpoint numpins 2; | |
12 | |
13 resistor_slot mapped_pins (side1, side2); | |
14 transistor_slot mapped_pins (E, B, C); | |
15 mosfet mapped_pins (G, S, D); | |
16 | |
17 /* TI packages */ | |
18 pkg_179GHH grid "pkg_179GHH.bgadef"; | |
19 pkg_100GGM grid "pkg_100GGM.bgadef"; | |
20 pkg_Rita_RF numpins 49; | |
21 pkg_TPA6203A1 mapped_pins (BYPASS, GND, In_neg, In_pos, SHUTDOWN, VDD, | |
22 Out_pos, Out_neg); | |
23 | |
24 /* non-TI RF components */ | |
25 pkg_RF3166 numpins 31; | |
26 pkg_M034F numpins 19; | |
27 | |
28 /* Flash+RAM MCP (two possibilities) */ | |
29 pkg_TLA064 grid "pkg_TLA064.bgadef"; | |
30 pkg_TLC056 grid "pkg_TLC056.bgadef"; | |
31 | |
32 /* crystal oscillator components */ | |
33 xtal_2pin_pkg numpins 2; | |
34 xtal_4pin_pkg numpins 4; | |
35 varactor_diode mapped_pins (Anode, Cathode); | |
36 | |
37 /* | |
38 * The reference design we are copying calls for a couple of RF chip | |
39 * attenuators. They are symmetrical in that pins 1 and 2 are equally | |
40 * suitable as either the input or the output, but the package shape is | |
41 * asymmetrical, thus it is a PCB layout decision which pin will be the | |
42 * input and which will be the output. | |
43 * | |
44 * We shall use a mapped_pins primitive and two different pinout mappings | |
45 * at the MCL binding stage, to be selected at layout time. | |
46 */ | |
47 | |
48 chip_attenuator mapped_pins (In, Out, GND1, GND2); | |
49 | |
50 /* connectors */ | |
51 header_2pin numpins 2; | |
52 conn_3pin numpins 3; | |
53 header_14pin numpins 14; | |
54 pkg_SMA_F numpins 5; | |
55 | |
56 /* misc peripherals */ | |
57 pkg_SIM_socket numpins 8; | |
58 basic_LED mapped_pins (Anode, Cathode); |