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comparison venus/src/core/S71PL129N.v @ 85:93b238ad7d6e

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first preparations for changing flash+RAM MCP to S71PL129N
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Dec 2021 05:58:58 +0000
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84:beb6519a3be5 85:93b238ad7d6e
1 module S71PL129N (Flash_Vcc, RAM_Vcc, Vss,
2 A, DQ, OE, WE,
3 Flash_CE1, Flash_CE2, Flash_RST,
4 Flash_WP_ACC, Flash_ready_busy,
5 RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB);
6
7 input Flash_Vcc, RAM_Vcc, Vss;
8 input [21:0] A;
9 inout [15:0] DQ;
10 input OE, WE;
11 input Flash_CE1, Flash_CE2, Flash_RST, Flash_WP_ACC;
12 output Flash_ready_busy;
13 input RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB;
14
15 /* instantiate the package; the mapping of signals to balls is defined here */
16
17 pkg_TLA064 pkg (.A1(), /* no connect */
18 .A10(), /* ditto */
19 .B5(), /* "" */
20 .B6(),
21 .C3(A[7]),
22 .C4(RAM_LB),
23 .C5(Flash_WP_ACC),
24 .C6(WE),
25 .C7(A[8]),
26 .C8(A[11]),
27 .D2(A[3]),
28 .D3(A[6]),
29 .D4(RAM_UB),
30 .D5(Flash_RST),
31 .D6(RAM_CE_acthigh),
32 .D7(A[19]),
33 .D8(A[12]),
34 .D9(A[15]),
35 .E2(A[2]),
36 .E3(A[5]),
37 .E4(A[18]),
38 .E5(Flash_ready_busy),
39 .E6(A[20]),
40 .E7(A[9]),
41 .E8(A[13]),
42 .E9(A[21]),
43 .F2(A[1]),
44 .F3(A[4]),
45 .F4(A[17]),
46 .F7(A[10]),
47 .F8(A[14]),
48 .F9(Flash_CE2),
49 .G2(A[0]),
50 .G3(Vss),
51 .G4(DQ[1]),
52 .G7(DQ[6]),
53 .G8(), /* no connect */
54 .G9(A[16]),
55 .H2(Flash_CE1),
56 .H3(OE),
57 .H4(DQ[9]),
58 .H5(DQ[3]),
59 .H6(DQ[4]),
60 .H7(DQ[13]),
61 .H8(DQ[15]),
62 .H9(), /* no connect */
63 .J2(RAM_CE_actlow),
64 .J3(DQ[0]),
65 .J4(DQ[10]),
66 .J5(Flash_Vcc),
67 .J6(RAM_Vcc),
68 .J7(DQ[12]),
69 .J8(DQ[7]),
70 .J9(Vss),
71 .K3(DQ[8]),
72 .K4(DQ[2]),
73 .K5(DQ[11]),
74 .K6(), /* no connect */
75 .K7(DQ[5]),
76 .K8(DQ[14]),
77 .L5(), /* no connect */
78 .L6(), /* ditto */
79 .M1(), /* "" */
80 .M10()
81 );
82
83 endmodule