FreeCalypso > hg > freecalypso-schem2
comparison venus/doc/MEMIF-fixed-2.8V @ 37:9c2f913fa5cf
venus/doc/MEMIF-fixed-2.8V: explanatory article
| author | Mychaela Falconia <falcon@freecalypso.org> |
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| date | Wed, 24 Nov 2021 18:14:11 +0000 |
| parents | |
| children | 711358516b55 |
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| 36:c1256c8757c3 | 37:9c2f913fa5cf |
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| 1 Our Calypso+Iota chipset allows Calypso MEMIF (memory bus interface) to run at | |
| 2 either 2.8V or 1.8V; the choice between these two voltages is made by way of | |
| 3 Iota VLMEM pin strapping. TI's Leonardo reference design had a pair of resistor | |
| 4 footprints connected to VLMEM (R209 pull-up for 2.8V and R210 pull-down for | |
| 5 1.8V), and both of these resistor footprints have been preserved by both | |
| 6 Openmoko and iWOW. Our FCDEV3B, based on Openmoko, has them too. All 3 boards | |
| 7 in question (OM GTA01/02, FCDEV3B and TR-800 module) use flash+RAM MCPs that run | |
| 8 at 2.8V, thus R209 is populated, R210 is unpopulated, and MEMIF runs at 2.8V. | |
| 9 | |
| 10 On FC Venus we have an additional complication: Calypso MEMIF goes not only to | |
| 11 the flash+RAM MCP, but also to our big color LCD. On the one hand our LCD | |
| 12 module does support split power supplies, with Vccio supporting the full range | |
| 13 from 1.65 to 3.6 V, and we could design our board to support both MEMIF voltage | |
| 14 options and thus both our current 2.8V flash+RAM MCP and hypothetical 1.8V | |
| 15 options. However, this design would imply additional complexity and cost: | |
| 16 | |
| 17 * We would need to run two power supply traces to our LCD: one trace to the LCD | |
| 18 module's Vcc pin (needs to be 2.5 V minimum) from our Vio rail (always 2.8V), | |
| 19 and another trace to the LCD module's Vccio pin from Iota VRMEM or VRRAM | |
| 20 regulator output (voltage switches with VLMEM strapping). | |
| 21 | |
| 22 * Because Calypso nRESET_OUT, which we use for LCD reset, is a 2.8V output | |
| 23 (V-IO domain, not MEMIF), we would need to insert a dual supply translating | |
| 24 buffer between this Calypso output and the LCD module's reset input. | |
| 25 | |
| 26 However, because the hypothetical possibility of swapping our current 2.8V | |
| 27 flash+RAM MCP for a 1.8V part is just that, hypothetical and not realistic, the | |
| 28 Mother's decision is to simplify our Venus board design by fixing MEMIF at 2.8V. | |
| 29 The simplifications resulting from this decision are as follows: | |
| 30 | |
| 31 * R209 and R210 are eliminated, Iota VLMEM is tied directly to UPR. | |
| 32 | |
| 33 * Only one 2.8V power supply trace will need to run to the LCD module; because | |
| 34 the module's Vcc and Vccio pins are directly adjacent on the FPC tail | |
| 35 interface, a single trace supplying both pins will be ideal. | |
| 36 | |
| 37 * No extra buffer IC on the connection from Calypso nRESET_OUT to the LCD | |
| 38 module's reset input, just a direct trace. | |
| 39 | |
| 40 * 2.8V supply for the LCD will be sourced from Vio (not VRMEM or VRRAM), | |
| 41 matching our previous Luna platform in which only Vio is available. | |
| 42 | |
| 43 When it comes to the flash+RAM MCP, we are being deliberately non-innovative: | |
| 44 rather than explore potentially suitable parts on our own, we copy specific | |
| 45 parts that have been used successfully in historical Calypso designs. On | |
| 46 FCDEV3B we copied Spansion S71PL129NC0HFW4B from Pirelli DP-L10, and the current | |
| 47 plan for FC Venus is to copy S71PL064JA0BFW0B (smaller footprint and no reset | |
| 48 complications like on FCDEV3B) from the TR-800 module. All of our potential MCP | |
| 49 choices from Spansion S71PL-J and S71PL-N families require a single supply | |
| 50 between 2.7 and 3.1 V, hence 2.8V MEMIF. |