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comparison venus/src/core/baseband.v @ 86:adc84e0e98d6

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add 74AXP1T34 buffer for flash reset
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Dec 2021 06:20:19 +0000
parents ec932276c8e6
children 148fab6e07e3
comparison
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85:93b238ad7d6e 86:adc84e0e98d6
3 * them. It approximately corresponds to the "200 - Baseband" sheet 3 * them. It approximately corresponds to the "200 - Baseband" sheet
4 * in the original Leonardo schematics. 4 * in the original Leonardo schematics.
5 */ 5 */
6 6
7 module baseband (GND, VBAT, VSIM, Vio, Vflash, Vsram, 7 module baseband (GND, VBAT, VSIM, Vio, Vflash, Vsram,
8 PWON, RPWON, nTESTRESET, ON_nOFF, CLKTCXO_IN, 8 PWON, RPWON, nTESTRESET, ON_nOFF, ON_nOFF_2V8, CLKTCXO_IN,
9 TDI, TDO, TCK, TMS, 9 TDI, TDO, TCK, TMS,
10 MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP, 10 MCU_A, MCU_D, MCU_RnW, MCU_nFWE, MCU_nFOE, MCU_FDP,
11 MCU_nBLE, MCU_nBHE, MCU_nCS, 11 MCU_nBLE, MCU_nBHE, MCU_nCS,
12 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1, 12 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
13 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA, 13 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
27 27
28 input GND, VBAT; 28 input GND, VBAT;
29 output VSIM, Vio, Vflash, Vsram; 29 output VSIM, Vio, Vflash, Vsram;
30 30
31 input PWON, RPWON, nTESTRESET; 31 input PWON, RPWON, nTESTRESET;
32 output ON_nOFF; 32 output ON_nOFF, ON_nOFF_2V8;
33 33
34 input CLKTCXO_IN; 34 input CLKTCXO_IN;
35 35
36 input TDI, TCK, TMS; 36 input TDI, TCK, TMS;
37 output TDO; 37 output TDO;
185 .MCUEN1_IO8(GPIO8), 185 .MCUEN1_IO8(GPIO8),
186 .MCUEN2_IO13(GPIO13), 186 .MCUEN2_IO13(GPIO13),
187 .SIM_IO(DBBSIO), 187 .SIM_IO(DBBSIO),
188 .SIM_CLK(DBBSCLK), 188 .SIM_CLK(DBBSCLK),
189 .SIM_RST(DBBSRST), 189 .SIM_RST(DBBSRST),
190 .SIM_CD(SIM_CD) 190 .SIM_CD(SIM_CD),
191 .ON_nOFF_2V8(ON_nOFF_2V8)
191 ); 192 );
192 193
193 abb_block abb ( .GND(GND), 194 abb_block abb ( .GND(GND),
194 .VBAT(VBAT), 195 .VBAT(VBAT),
195 .VSIM(VSIM), 196 .VSIM(VSIM),