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comparison venus/src/top/mobile.v @ 19:ae08caf957d7

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venus/src/top/mobile.v written
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 20 Nov 2021 05:45:37 +0000
parents
children 85fbd582af88
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18:2f344ca2c1e4 19:ae08caf957d7
1 /*
2 * This Verilog module is the top level for the mobile domain of FC Venus,
3 * i.e., everything that isn't in the USB domain.
4 */
5
6 module mobile (GND, VCHG, Host_TxD, Host_RxD, Host_RTS, Host_CTS,
7 Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2,
8 RPWON, nTESTRESET);
9
10 input GND, VCHG;
11 input Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
12 output Host_RxD, Host_CTS, Host_DCD, Host_RI, Host_RxD2;
13 input RPWON, nTESTRESET;
14
15 /* all wires for the top level of the mobile domain */
16
17 wire VBAT, VSIM, Vio;
18
19 wire PWON, ON_nOFF;
20
21 wire TDI, TCK, TMS, TDO;
22
23 wire [22:0] MCU_A;
24 wire [15:0] MCU_D;
25 wire MCU_RnW, MCU_nFWE, MCU_nFOE;
26 wire LCD_CS, LCD_RESET;
27
28 wire GPIO1_SPKR, GPIO3_DTR, GPIO6_headset;
29 wire BL_GPIO9, BL_GPIO10, BL_GPIO11, BL_GPIO12;
30
31 wire RX_IRDA, RX_MODEM, CTS_MODEM;
32
33 wire [4:0] KBC, KBR;
34 wire DSR_LPG, BU_PWT, LT_PWL;
35
36 wire ADIN1, ADIN2, ADIN3;
37
38 wire AUXI, AUXON, AUXOP;
39 wire EARN, EARP;
40 wire HSMICBIAS, HSO, HSMICP;
41 wire MICBIAS, MICIN, MICIP;
42
43 wire LED_B; /* ueda blemish */
44 wire LED_C; /* actually used */
45
46 wire ICTL, PCHG, VBATS, VCCS;
47
48 wire SIM_CLK, SIM_RST, SIM_IO, SIM_CD;
49 wire ANTENNA;
50
51 /* instantiate the core */
52
53 core core (.GND(GND),
54 .VBAT1(VBAT),
55 .VBAT2(VBAT),
56 .VBAT3(VBAT),
57 .VSIM(VSIM),
58 .Vio(Vio),
59 .PWON(PWON),
60 .RPWON(RPWON),
61 .nTESTRESET(nTESTRESET),
62 .ON_nOFF(ON_nOFF),
63 .TDI(TDI),
64 .TDO(TDO),
65 .TCK(TCK),
66 .TMS(TMS),
67 .MCU_A(MCU_A),
68 .MCU_D(MCU_D),
69 .MCU_RnW(MCU_RnW),
70 .MCU_nFWE(MCU_nFWE),
71 .MCU_nFOE(MCU_nFOE),
72 .EXT_nCS3(LCD_CS),
73 .EXT_nCS4(), /* not used on FC Venus */
74 /* uWire/I2C interface unused */
75 .SCLK(),
76 .SDO(),
77 .SDI_SDA(),
78 .nSCS0_SCL(),
79 .nSCS1(),
80 /* Calypso UARTs */
81 .TX_IRDA(Host_RxD2),
82 .RX_IRDA(RX_IRDA),
83 .TXIR_IRDA(),
84 .RXIR_IRDA(GND),
85 .SD_IRDA(),
86 .TX_MODEM(Host_RxD),
87 .RX_MODEM(RX_MODEM),
88 .RTS_MODEM(Host_CTS),
89 .CTS_MODEM(CTS_MODEM),
90 .DSR_LPG(DSR_LPG),
91 /* MCSI pins are GPIOs on this board, backlight control */
92 .MCSI_TXD(BL_GPIO9),
93 .MCSI_RXD(BL_GPIO10),
94 .MCSI_CLK(BL_GPIO11),
95 .MCSI_FSYNCH(BL_GPIO12),
96 .KBC(KBC),
97 .KBR(KBR),
98 .BU_PWT(BU_PWT),
99 .LT_PWL(LT_PWL),
100 .GPIO0(),
101 .GPIO1(GPIO1_SPKR),
102 .GPIO2(Host_DCD),
103 .GPIO3(GPIO3_DTR),
104 .GPIO4(),
105 .GPIO6(GPIO6_headset),
106 .GPIO7_RESETOUT(LCD_RESET),
107 .GPIO8(Host_RI),
108 .GPIO13(),
109 .ADIN1(ADIN1),
110 .ADIN2(ADIN2),
111 .ADIN3(ADIN3),
112 .DAC(),
113 .AUXI(AUXI),
114 .AUXON(AUXON),
115 .AUXOP(AUXOP),
116 .EARN(EARN),
117 .EARP(EARP),
118 .HSMICBIAS(HSMICBIAS),
119 .HSMICP(HSMICP),
120 .HSO(HSO),
121 .MICBIAS(MICBIAS),
122 .MICIN(MICIN),
123 .MICIP(MICIP),
124 .LED_A(),
125 .LED_B(LED_B),
126 .LED_C(LED_C),
127 .ICTL(ICTL),
128 .PCHG(PCHG),
129 .VBATS(VBATS),
130 .VCCS(VCCS),
131 .VCHG(VCHG),
132 .SIM_IO(SIM_IO),
133 .SIM_CLK(SIM_CLK),
134 .SIM_RST(SIM_RST),
135 .SIM_CD(SIM_CD),
136 .ANTENNA(ANTENNA)
137 );
138
139 /* battery or lab bench power input */
140 battery batt (.VBAT(VBAT),
141 .GND(GND),
142 .Third_pin(ADIN2)
143 );
144
145 /* Calypso UART inputs */
146 calypso_uart_in uart ( .GND(GND),
147 .VBAT(VBAT),
148 .Vio(Vio),
149 .Host_TxD(Host_TxD),
150 .Host_RTS(Host_RTS),
151 .Host_DTR(Host_DTR),
152 .Host_TxD2(Host_TxD2),
153 .RX_MODEM(RX_MODEM),
154 .CTS_MODEM(CTS_MODEM),
155 .GPIO_DTR(GPIO3_DTR),
156 .RX_IRDA(RX_IRDA)
157 );
158
159 /* JTAG interface */
160 jtag_if jtag_if (.GND(GND),
161 .Vio(Vio),
162 .nTESTRESET(nTESTRESET),
163 .TDI(TDI),
164 .TCK(TCK),
165 .TMS(TMS),
166 .TDO(TDO)
167 );
168
169 /* SIM socket */
170 sim_socket_block sim (.GND(GND),
171 .Vio(Vio),
172 .VSIM(VSIM),
173 .SIM_CLK(SIM_CLK),
174 .SIM_RST(SIM_RST),
175 .SIM_IO(SIM_IO),
176 .SIM_CD(SIM_CD)
177 );
178
179 /* antenna interface */
180 sma_wrap SMA (.Center(ANTENNA), .Shell(GND));
181
182 endmodule