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comparison venus/src/periph/lcd_subsystem.v @ 48:d55824058cfc

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LCD subsystem integrated
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 27 Nov 2021 02:46:19 +0000
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47:9f5a3567d699 48:d55824058cfc
1 module lcd_subsystem (GND, VBAT, Vio, DB, RD, WR, RS, CS, RESET,
2 BL_GPIO9, BL_GPIO11, BL_GPIO12);
3
4 input GND, VBAT, Vio;
5
6 inout [15:0] DB;
7 input RD, WR, RS, CS, RESET;
8
9 input BL_GPIO9, BL_GPIO11, BL_GPIO12;
10
11 wire [1:3] LEDK;
12
13 lcd_module lcd (.GND(GND),
14 .VCI(Vio),
15 .IOVCC(Vio),
16 .DB(DB),
17 .RD(RD),
18 .WR(WR),
19 .RS(RS),
20 .CS(CS),
21 .RESET(RESET),
22 .IM0(GND),
23 .LEDA(VBAT),
24 /* LEDK broken out to allow reordering for layout */
25 .LEDK[1](LEDK[1]),
26 .LEDK[2](LEDK[2]),
27 .LEDK[3](LEDK[3])
28 );
29
30 capacitor LCD_bypass_cap (Vio, GND);
31
32 bl_current_sink bl (.GND(GND),
33 .Vio(Vio),
34 .BL_GPIO9(BL_GPIO9),
35 .BL_GPIO11(BL_GPIO11),
36 .BL_GPIO12(BL_GPIO12),
37 /* LEDK broken out to allow reordering for layout */
38 .LEDK[1](LEDK[1]),
39 .LEDK[2](LEDK[2]),
40 .LEDK[3](LEDK[3])
41 );
42
43 endmodule