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diff venus/src/core/M034F.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/M034F.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,35 @@
+module M034F (ANT, GND, RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2,
+		TX_LOW, TX_HIGH, V_TX_LOW, V_TX_HIGH, V_RX_850);
+
+inout ANT;
+input GND;
+
+output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2;
+input TX_LOW, TX_HIGH;
+
+input V_TX_LOW, V_TX_HIGH, V_RX_850;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_M034F pkg  (.pin_1(ANT),
+		.pin_2(GND),
+		.pin_3(TX_HIGH),
+		.pin_4(GND),
+		.pin_5(GND),
+		.pin_6(TX_LOW),
+		.pin_7(V_TX_LOW),
+		.pin_8(V_TX_HIGH),
+		.pin_9(V_RX_850),
+		.pin_10(RX_DCS1),
+		.pin_11(RX_DCS2),
+		.pin_12(RX_PCS1),
+		.pin_13(RX_PCS2),
+		.pin_14(RX_LOW1),
+		.pin_15(RX_LOW2),
+		.pin_16(GND),
+		.pin_17(GND),
+		.pin_18(GND),
+		.pin_19(GND)
+	);
+
+endmodule