FreeCalypso > hg > freecalypso-schem2

diff venus/src/core/memory.v @ 9:3ed0f7a9c489

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children 96e02b1b2374
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/memory.v	Fri Nov 19 05:58:21 2021 +0000
@@ -0,0 +1,33 @@
+module memory  (GND, Vflash, Vsram,
+		MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE,
+		Flash_RST, CS_flash1, CS_RAM);
+
+input GND, Vflash, Vsram;
+input [22:1] MCU_A;
+inout [15:0] MCU_D;
+input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE;
+input Flash_RST;
+input CS_flash1, CS_RAM;
+
+S71PL064J chip (.Flash_Vcc(Vflash),
+		.RAM_Vcc(Vsram),
+		.Vss(GND),
+		.A(MCU_A),
+		.DQ(MCU_D),
+		.OE(MCU_nRD),
+		.WE(MCU_nWR),
+		.Flash_CE1(CS_flash1),
+		.Flash_RST(Flash_RST),
+		.Flash_WP_ACC(Vflash),
+		.Flash_ready_busy(),	/* no connect */
+		.RAM_CE_actlow(CS_RAM),
+		.RAM_CE_acthigh(Vsram),
+		.RAM_UB(MCU_nBHE),
+		.RAM_LB(MCU_nBLE)
+	);
+
+/* bypass caps */
+capacitor C318 (Vsram, GND);
+capacitor C322 (Vflash, GND);
+
+endmodule