FreeCalypso > hg > freecalypso-schem2
diff venus/src/core/rf_fem_block.v @ 9:3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 19 Nov 2021 05:58:21 +0000 |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/venus/src/core/rf_fem_block.v Fri Nov 19 05:58:21 2021 +0000 @@ -0,0 +1,50 @@ +/* + * This module encapsulates the RF FEM (quadband M034F) along with the PNP + * transistors and R/C footprints to GND for the control lines, and the cap + * on the antenna output. + */ + +module rf_fem_block (GND, VREG3, Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850, + RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2, + TX_LOW, TX_HIGH, ANT); + +input GND, VREG3; +input Ctrl_Tx_Low, Ctrl_Tx_High, Ctrl_Rx_850; + +output RX_LOW1, RX_LOW2, RX_DCS1, RX_DCS2, RX_PCS1, RX_PCS2; +input TX_LOW, TX_HIGH; +inout ANT; + +wire ANT_before_cap; +wire V_TX_LOW, V_TX_HIGH, V_RX_850; + +/* transform control signals through PNP transistors */ + +transistor_slot PNP_FEM7 (.E(VREG3), .B(Ctrl_Tx_Low), .C(V_TX_LOW)); +transistor_slot PNP_FEM8 (.E(VREG3), .B(Ctrl_Tx_High), .C(V_TX_HIGH)); +transistor_slot PNP_FEM9 (.E(VREG3), .B(Ctrl_Rx_850), .C(V_RX_850)); + +/* instantiate the M034F */ + +M034F M034F (.ANT(ANT_before_cap), + .GND(GND), + .RX_LOW1(RX_LOW1), + .RX_LOW2(RX_LOW2), + .RX_DCS1(RX_DCS1), + .RX_DCS2(RX_DCS2), + .RX_PCS1(RX_PCS1), + .RX_PCS2(RX_PCS2), + .TX_LOW(TX_LOW), + .TX_HIGH(TX_HIGH), + .V_TX_LOW(V_TX_LOW), + .V_TX_HIGH(V_TX_HIGH), + .V_RX_850(V_RX_850) + ); + +capacitor C635 (ANT_before_cap, ANT); + +capacitor C645 (V_TX_LOW, GND); +capacitor C644 (V_TX_HIGH, GND); +capacitor C643 (V_RX_850, GND); + +endmodule