--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/sim_socket_block.v	Fri Nov 19 20:59:14 2021 +0000
@@ -0,0 +1,38 @@
+/*
+ * This module encapsulates the complete SIM socket block:
+ * the actual socket, the bypass cap and our SIM_CD circuit.
+ */
+
+module sim_socket_block (GND, Vio, VSIM, SIM_CLK, SIM_RST, SIM_IO, SIM_CD);
+
+input GND, Vio, VSIM;
+input SIM_CLK, SIM_RST;
+inout SIM_IO;
+output SIM_CD;
+
+wire SIM_CD_inverted;
+
+sim_socket_wrap socket (.C1(VSIM),
+			.C2(SIM_RST),
+			.C3(SIM_CLK),
+			.C5(GND),
+			.C6(VSIM),
+			.C7(SIM_IO),
+			.SW1(GND),
+			.SW2(SIM_CD_inverted)
+		);
+
+/* cap per Leonardo schematics */
+capacitor C306 (VSIM, GND);
+
+/* pull-up on the switch line */
+resistor switch_pullup (SIM_CD_inverted, Vio);
+
+/* inverting buffer for SIM_CD */
+inv_buffer_74LVC1G04 inv (.GND(GND),
+			  .Vcc(Vio),
+			  .A(SIM_CD_inverted),
+			  .Y(SIM_CD)
+		);
+
+endmodule