module rita_rf_chip (GND,
		     CLK, DATA, STROBE, RESETZ,
		     IN, IP, QN, QP,
		     LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP,
		     LBTXOUT, HBTXOUT,
		     DAC, DET1, DET2, APC,
		     RTEMP_VTEST, SIOUT_TST, TSTVCO1, TSTVCO2,
		     VBAT1, VBAT2, VREG1, VREG2, VREG3, VRIO,
		     VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9,
		     VCC10, VCC11, VCC12, VCC13, VBG,
		     XEN, XSEL, XIN, XOUT);

input GND;
input CLK, DATA, STROBE, RESETZ;
inout IN, IP, QN, QP;

input LNAGSMN, LNAGSMP, LNADCSN, LNADCSP, LNAPCSN, LNAPCSP;
output LBTXOUT, HBTXOUT;

input DAC, DET1, DET2;
output APC;

output RTEMP_VTEST, SIOUT_TST, TSTVCO1, TSTVCO2;

input VBAT1, VBAT2, VRIO;
output VREG1, VREG2, VREG3;
inout VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9;
inout VCC10, VCC11, VCC12, VCC13, VBG;

input XEN, XSEL;
inout XIN;
output XOUT;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_Rita_RF pkg (.pin_1(XSEL),
		 .pin_2(XEN),
		 .pin_3(RESETZ),
		 .pin_4(VCC1),
		 .pin_5(DATA),
		 .pin_6(VCC2),
		 .pin_7(CLK),
		 .pin_8(VCC3),
		 .pin_9(STROBE),
		.pin_10(VCC4),
		.pin_11(VCC5),
		.pin_12(VCC6),
		.pin_13(SIOUT_TST),
		.pin_14(RTEMP_VTEST),
		.pin_15(LNAPCSP),
		.pin_16(LNAPCSN),
		.pin_17(VCC7),
		.pin_18(LNADCSP),
		.pin_19(LNADCSN),
		.pin_20(VBG),
		.pin_21(LNAGSMP),
		.pin_22(LNAGSMN),
		.pin_23(VREG3),
		.pin_24(VBAT2),
		.pin_25(DET1),
		.pin_26(DET2),
		.pin_27(APC),
		.pin_28(DAC),
		.pin_29(HBTXOUT),
		.pin_30(VCC8),
		.pin_31(LBTXOUT),
		.pin_32(VCC9),
		.pin_33(VCC10),
		.pin_34(TSTVCO1),
		.pin_35(TSTVCO2),
		.pin_36(VCC11),
		.pin_37(VCC12),
		.pin_38(IN),
		.pin_39(IP),
		.pin_40(QP),
		.pin_41(QN),
		.pin_42(VCC13),
		.pin_43(VREG1),
		.pin_44(VBAT1),
		.pin_45(VREG2),
		.pin_46(VRIO),
		.pin_47(XOUT),
		.pin_48(XIN),
		.pin_49(GND)
	);

endmodule