/*
 * This Verilog module captures our JTAG interface circuit, copied from
 * Leonardo and FCDEV3B.  Unlike FCDEV3B, for the present FC Venus version
 * we omit TI's non-understood EMU0/1 signals.  In our defense, Leonardo
 * schematics also show EMU0/1 as unconnected, with only the JTAG scan chain
 * and XDS_RESET brought out.
 */

module jtag_if (GND, Vio, nTESTRESET, TDI, TCK, TMS, TDO);

input GND, Vio;

inout nTESTRESET;

output TDI, TCK, TMS;
input TDO;

wire XDS_RESET, between_transistors;

header_14pin connector (.pin_1(TMS),
			.pin_2(XDS_RESET),
			.pin_3(TDI),
			.pin_4(GND),
			.pin_5(Vio),
			.pin_6(),	/* keying position */
			.pin_7(TDO),
			.pin_8(GND),
			.pin_9(TCK),
			.pin_10(GND),
			.pin_11(TCK),
			.pin_12(GND),
			.pin_13(),	/* EMU0 omitted */
			.pin_14()	/* EMU1 omitted */
	);

capacitor C363 (Vio, GND);

/* pull-up/down resistors */
resistor_slot R361A (TCK, GND);
/* skipping TDO (R361B) */
resistor_slot R361C (TDI, Vio);
resistor_slot R361D (TMS, Vio);

/* reset circuit */
capacitor C335 (Vio, XDS_RESET);
transistor_slot PNP (.E(Vio),
		     .B(XDS_RESET),
		     .C(between_transistors)
	);
transistor_slot NPN (.E(GND),
		     .B(between_transistors),
		     .C(nTESTRESET)
	);

endmodule