/*
 * This Verilog module encapsulates our secondary headset audio channel,
 * connected to Iota headset interface.
 */

module audio_hso (GND, Vio, HSMICBIAS, HSMICP, HSO, Detect);

input GND, Vio;
input HSO, HSMICBIAS;
output HSMICP, Detect;

/* internal wires */

wire EAR_jack, MIC_jack;

/* instantiate the jack */

trrs_jack jack (.T(GND),
		.R(MIC_jack),
		.R2(EAR_jack),
		.S(GND),
		.T_sw(Detect),
		.R_sw()		/* not used */
	);

/* output path */

capacitor HSO_cap (HSO, EAR_jack);

/* microphone input circuit */

capacitor C37 (HSMICBIAS, GND);
resistor R19 (HSMICBIAS, MIC_jack);

capacitor C38 (MIC_jack, GND);

capacitor C23 (MIC_jack, HSMICP);
capacitor C22 (HSMICP, GND);

/* Detect pull-up resistor */

resistor Detect_pullup (Detect, Vio);

endmodule