view venus/doc/Star-points-in-core @ 89:30f567edd2b6

add option of reverting to Calypso FDP for flash reset
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 10 Dec 2021 22:40:08 +0000
parents 971c05950675
children
line wrap: on
line source

iWOW's TR-800 module, whose reverse-engineered PCB layout will serve as a
reference for the Calypso core of FC Venus, is nothing but a mass-produced
version of TI's Leonardo reference design.  We don't have any original PCB
layout files for Leonardo, but we do have schematics, in 3 different versions:

ftp://ftp.freecalypso.org/pub/GSM/Calypso/Leonardo_plus_RD122.pdf
ftp://ftp.freecalypso.org/pub/GSM/Calypso/Leonardo_plus_quadband_schem.pdf
ftp://ftp.freecalypso.org/pub/GSM/Calypso/Leonardo_rev05.pdf

TR-800 is based on quadband Leonardo+ (that's what makes it interesting), but
the hobbled 2-band version of Leonardo is the only one for which we have TI's
original DSN (OrCAD) schematic file, in addition to the corresponding PDF:

ftp://ftp.freecalypso.org/pub/GSM/Calypso/Leonardo_rev05.dsn

TI's group in Aalborg (Denmark) that designed and built their development boards
used OrCAD for schematics and PADS for PCB layout.  We have their PADS PCB
design file for a different board from about the same time frame (E-Sample),
but not for any Leonardo variant.

If you look at the baseband page of Leonardo schematics (this part is the same
in all 3 versions), you will see 3 symbols denoting star routing: HST201 and
HST202 (labeled "STAR_CONFIG") split V-DBB net into VDD-PLL and VDD-CORE
branches, and HST203 (labeled "GND_POINT") creates a special ground for the
32.768 kHz oscillator circuit, connected to the rest of board ground at just
one point.

This star routing in TI's reference version of Calypso/Leonardo core exists not
only in TI's schematics, but also in the physical PCB layout which we have
recovered from TR-800 by reverse engineering.  If you look at the Gerber files
which we received from the PCB RE company (published on our FTP site in 2021),
specifically the OKPCBM~1.G1 gerber file corresponding to the inner layer just
below the surface (L2 or L5 depending on which way you count), you can see the
physical features that were once produced, presumably in PADS, to effect the
star routing depicted in the schematics.

The physical PCB star routing feature corresponding to HST201 & HST202 resides
just underneath C214 footprint.  There is a microvia (blind via going only one
layer in) inside C214 pad 1 (the left pad in the Gerber view), and on the inner
layer where this microvia goes, one can clearly see the feature that splits the
V-DBB net coming from C214.1 into VDD-PLL and VDD-CORE branches.  The lower (in
the Gerber view) branch that goes to two microvias back to the surface is
VDD-PLL, whereas the other branch that goes to an inner buried via (spanning L2
through L5) is VDD-CORE.

The other star routing feature in the TR-800 PCB corresponding to TI's HST203
can be seen in the far lower right corner of the same OKPCBM~1.G1 gerber file:
look for an L shape that connects a short thin trace (going to a microvia to the
surface) to the surrounding GND copper pour.  The short thin trace connected to
the GND copper pour by the L shape is what we named GND_32khz in
src/core/dbb_block.v, and the L shape on the inner layer is what eventually
became of HST203.

The present ueda netlist source code for FC Venus is written with the
expectation that the same pseudo-component EDA trick for star routing will be
used on our board, using intnoconn feature of pcb-rnd:

http://repo.hu/cgi-bin/pool.cgi?project=pcb-rnd&cmd=show&node=intnoconn

There is one difference in this regard between TI's original version and ours.
In TI's original version all 3 pseudo-component objects HST201, HST202 and
HST203 were 2-way stars, with HST201 and HST202 being somehow combined in PADS
layout to form the desired 3-way star.  In our version 3-way star HST200
explicitly replaces TI's HST201+HST202 pair.  The actual pcb-rnd subcircuits
for the 3-way star HST200 and the 2-way star HST203 will need to be created by
the PCB layout engineer.