view venus/src/periph/trrs_jack.v @ 57:3afd172b83e1

main audio channel implemented
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 02:22:39 +0000
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/*
 * This Verilog module encapsulates the physical PCB footprint pinout
 * of the TRRS jack part we are using.
 */

module trrs_jack (T, R, R2, S, T_sw, R_sw);

inout T, R, R2, S;
inout T_sw, R_sw;

pkg_TRRS_jack pkg (.pin_1(S),
		   .pin_2(T),
		   .pin_3(R),
		   .pin_4(R2),
		   .pin_5(T_sw),
		   .pin_6(R_sw)
	);

endmodule