module calypso_179ghh (TSPCLKX, TSPDO, TSPDI_IO4, TSPEN, TSPACT,
			DATA, ADD, RnW, nFWE, nFOE, FDP, nBLE, nBHE, nCS,
			VDDS_MIF, VDDS_1, VDDS_2, VDD, VSS,
			VDDS_RTC, VDD_RTC, VSS_RTC,
			VDD_ANG, VSS_ANG, VDD_PLL, VSS_PLL,
			SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
			TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
			TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
			MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
			KBC, KBR, BU_PWT, LT_PWL, GPIO,
			nRESET_OUT_IO7, nIBOOT, IDDQ,
			CLKTCXO, VSSO, OSC32K_IN, OSC32K_OUT,
			CLK32K_OUT, CLK13M_OUT, nRESPWON, EXT_FIQ, EXT_IRQ,
			TCXOEN, RFEN, ON_OFF, IT_WAKEUP,
			nEMU, nBSCAN, TDI, TDO, TCK, TMS,
			BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
			VDX, VDR, VFSRX, VCLKRX,
			MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
			SIM_IO, SIM_CLK, SIM_RST, SIM_CD, SIM_PWCTRL_IO5);

output TSPCLKX, TSPDO;
inout TSPDI_IO4;
output [3:0] TSPEN;
output [11:0] TSPACT;

inout [15:0] DATA;
output [22:0] ADD;
output RnW, nFWE, nFOE, FDP, nBLE, nBHE;
output [4:0] nCS;

input VDDS_MIF, VDDS_1, VDDS_2, VDD, VSS;
input VDDS_RTC, VDD_RTC, VSS_RTC;
input VDD_ANG, VSS_ANG, VDD_PLL, VSS_PLL;

output SCLK, SDO, nSCS1;
inout SDI_SDA, nSCS0_SCL;

output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
inout DSR_LPG;

output MCSI_TXD;
input MCSI_RXD;
inout MCSI_CLK, MCSI_FSYNCH;

output [4:0] KBC;
input [4:0] KBR;
output BU_PWT, LT_PWL;
inout [3:0] GPIO;

output nRESET_OUT_IO7;
input nIBOOT, IDDQ, CLKTCXO, VSSO;
inout OSC32K_IN, OSC32K_OUT;
output CLK32K_OUT, CLK13M_OUT;
input nRESPWON, EXT_FIQ, EXT_IRQ;

output TCXOEN, RFEN, IT_WAKEUP;
input ON_OFF;

inout [1:0] nEMU;
input nBSCAN, TDI, TCK, TMS;
output TDO;

input BFSR, BDR;
output BFSX, BDX;
inout BCLKX_IO6;
input BCLKR_ARMCLK;

output VDX;
input VDR, VFSRX, VCLKRX;

input MCUDI;
output MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13;

inout SIM_IO, SIM_PWCTRL_IO5;
output SIM_CLK, SIM_RST;
input SIM_CD;

/* instantiate the package; the mapping of signals to balls is defined here */

pkg_179GHH pkg (.F3(ADD[0]),
		.F2(ADD[1]),
		.G5(ADD[2]),
		.G4(ADD[3]),
		.G2(ADD[4]),
		.G3(ADD[5]),
		.H1(ADD[6]),
		.H3(ADD[7]),
		.H2(ADD[8]),
		.H4(ADD[9]),
		.H5(ADD[10]),
		.J1(ADD[11]),
		.J2(ADD[12]),
		.J3(ADD[13]),
		.J4(ADD[14]),
		.K3(ADD[15]),
		.K2(ADD[16]),
		.K4(ADD[17]),
		.J5(ADD[18]),
		.L1(ADD[19]),
		.L2(ADD[20]),
		.L3(ADD[21]),
		.D2(ADD[22]),
		.B7(DATA[0]),
		.D7(DATA[1]),
		.E7(DATA[2]),
		.D6(DATA[3]),
		.A6(DATA[4]),
		.C6(DATA[5]),
		.E6(DATA[6]),
		.C5(DATA[7]),
		.B5(DATA[8]),
		.D5(DATA[9]),
		.E5(DATA[10]),
		.B4(DATA[11]),
		.C4(DATA[12]),
		.D4(DATA[13]),
		.A3(DATA[14]),
		.B3(DATA[15]),
		.F4(FDP),
		.B2(RnW),
		.F5(nBHE),
		.E4(nBLE),
		.C2(nCS[0]),
		.C3(nCS[1]),
		.C1(nCS[2]),
		.D3(nCS[3]),
		.C11(nCS[4]),
		.E2(nFOE),
		.E3(nFWE),
		.J14(TSPCLKX),
		.H10(TSPDI_IO4),
		.H11(TSPDO),
		.H13(TSPEN[0]),
		.H12(TSPEN[1]),
		.H14(TSPEN[2]),
		.G12(TSPEN[3]),
		.M12(TSPACT[0]),
		.M14(TSPACT[1]),
		.L12(TSPACT[2]),
		.L13(TSPACT[3]),
		.J10(TSPACT[4]),
		.K11(TSPACT[5]),
		.K13(TSPACT[6]),
		.K12(TSPACT[7]),
		.K14(TSPACT[8]),
		.J11(TSPACT[9]),
		.J12(TSPACT[10]),
		.J13(TSPACT[11]),
		.P9(SCLK),
		.M9(SDI_SDA),
		.K8(SDO),
		.L9(nSCS0_SCL),
		.N9(nSCS1),
		.C8(TX_IRDA),
		.D8(RX_IRDA),
		.C7(TXIR_IRDA),
		.A8(RXIR_IRDA),
		.B8(SD_IRDA),
		.B9(TX_MODEM),
		.A9(RX_MODEM),
		.E8(RTS_MODEM),
		.D9(DSR_LPG),
		.C9(CTS_MODEM),
		.L10(MCSI_TXD),
		.M10(MCSI_RXD),
		.N10(MCSI_CLK),
		.K9(MCSI_FSYNCH),
		.N4(KBC[0]),
		.K5(KBC[1]),
		.L5(KBC[2]),
		.P5(KBC[3]),
		.M5(KBC[4]),
		.K6(KBR[0]),
		.M6(KBR[1]),
		.P6(KBR[2]),
		.N6(KBR[3]),
		.L6(KBR[4]),
		.K7(BU_PWT),
		.L7(LT_PWL),
		.N3(GPIO[0]),
		.P3(GPIO[1]),
		.L4(GPIO[2]),
		.M4(GPIO[3]),
		.N2(nRESET_OUT_IO7),
		.N1(nIBOOT),
		.M2(IDDQ),
		.E13(CLKTCXO),
		.C13(OSC32K_IN),
		.B13(OSC32K_OUT),
		.C12(CLK32K_OUT),
		.F12(CLK13M_OUT),
		.D12(nRESPWON),
		.P1(EXT_FIQ),
		.M3(EXT_IRQ),
		.A4(VDDS_MIF),
		.B6(VDDS_MIF),
		.G1(VDDS_MIF),
		.D1(VDDS_MIF),
		.A11(VDDS_2),
		.L14(VDDS_1),
		.N5(VDDS_1),
		.A5(VDD),
		.B12(VDD),
		.N14(VDD),
		.P7(VDD),
		.M1(VDD),
		.E1(VDD),
		.F1(VSS),
		.N8(VSS),
		.K1(VSS),
		.P2(VSS),
		.P4(VSS),
		.P10(VSS),
		.P13(VSS),
		.G14(VSS),
		.A10(VSS),
		.A7(VSS),
		.A2(VSS),
		.B1(VSS),
		.D13(VDDS_RTC),
		.D14(VDD_RTC),
		.C14(VSS_RTC),
		.E11(VDD_ANG),
		.E12(VSS_ANG),
		.F11(VDD_PLL),
		.E14(VSS_PLL),
		.A14(VSSO),
		.A12(TCXOEN),
		.A13(RFEN),
		.F10(ON_OFF),
		.B14(IT_WAKEUP),
		.D11(nBSCAN),
		.B11(nEMU[0]),
		.E10(nEMU[1]),
		.D10(TDI),
		.C10(TDO),
		.B10(TCK),
		.E9(TMS),
		.L11(BFSR),
		.K10(BDR),
		.P12(BFSX),
		.M11(BDX),
		.P11(BCLKR_ARMCLK),
		.N11(BCLKX_IO6),
		.P14(VDX),
		.N13(VDR),
		.M13(VFSRX),
		.N12(VCLKRX),
		.N7(MCUDI),
		.M7(MCUDO),
		.M8(MCUEN0),
		.P8(MCUEN1_IO8),
		.L8(MCUEN2_IO13),
		.G13(SIM_IO),
		.F13(SIM_CLK),
		.G10(SIM_RST),
		.G11(SIM_CD),
		.F14(SIM_PWCTRL_IO5)
	);

endmodule